From e16de95dce32f077361577377d5c52fc4ad78339 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Fri, 7 Aug 2026 02:15:09 +0800 Subject: [RISCV] Add generated RV64GC register description Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling. --- backend/unittests/Target/TestTarget.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'backend/unittests/Target/TestTarget.cpp') diff --git a/backend/unittests/Target/TestTarget.cpp b/backend/unittests/Target/TestTarget.cpp index 4d31fb9..a367454 100644 --- a/backend/unittests/Target/TestTarget.cpp +++ b/backend/unittests/Target/TestTarget.cpp @@ -25,7 +25,8 @@ namespace { [[nodiscard]] PhysicalRegisterDesc physicalRegister(std::uint32_t Number, const char *Name, std::uint32_t Encoding, std::vector Units) { - return PhysicalRegisterDesc{phys(Number), Name, Encoding, std::move(Units)}; + return PhysicalRegisterDesc{phys(Number), Name, Encoding, std::move(Units), + false, false, false, {}}; } [[nodiscard]] RegisterClassDesc -- cgit v1.2.3