From 220c9cd426ec0590f6a43550b28fb344d8dfd8fd Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sat, 15 Aug 2026 19:04:08 +0800 Subject: [RISCV][GlobalISel] Legalize floating-point to integer conversions --- backend/utils/TableGen/Common/CodeGenInstruction.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'backend/utils/TableGen/Common/CodeGenInstruction.cpp') diff --git a/backend/utils/TableGen/Common/CodeGenInstruction.cpp b/backend/utils/TableGen/Common/CodeGenInstruction.cpp index cabe8d4..c314304 100644 --- a/backend/utils/TableGen/Common/CodeGenInstruction.cpp +++ b/backend/utils/TableGen/Common/CodeGenInstruction.cpp @@ -287,6 +287,10 @@ pipelineStageEnumerator(std::string_view Value) noexcept { fail(InputOperand.Range, "register definition operands must accept only registers"); return false; } + if (InputOperand.TypeIndex && !IsRegisterOnly) { + fail(InputOperand.Range, "instruction operand type_index requires exactly one register kind"); + return false; + } if (!HasRegisterKind && (InputOperand.RegisterClassSymbol || InputOperand.RegisterBankSymbol || InputOperand.EarlyClobber || InputOperand.AllowSubReg)) { fail(InputOperand.Range, "non-register operands cannot have register constraints"); @@ -337,6 +341,7 @@ pipelineStageEnumerator(std::string_view Value) noexcept { Result.Optional = InputOperand.Optional; Result.VariadicGroup = InputOperand.VariadicGroup; Result.AllowSubReg = InputOperand.AllowSubReg; + Result.TypeIndex = InputOperand.TypeIndex; Result.AllowedTargetFlags = InputOperand.AllowedTargetFlags; return true; } @@ -529,6 +534,14 @@ CodeGenTarget::normalizeImplicitRegisters(const std::vector