From 6c97d54954112be9a5badacaec8efa1d05bd7d15 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Wed, 19 Aug 2026 02:50:30 +0800
Subject: [RISCV][GlobalISel] Generate indirect branch selection

---
 backend/utils/TableGen/Common/CodeGenTarget.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'backend/utils/TableGen/Common/CodeGenTarget.h')

diff --git a/backend/utils/TableGen/Common/CodeGenTarget.h b/backend/utils/TableGen/Common/CodeGenTarget.h
index 97e1447..9a7c0a2 100644
--- a/backend/utils/TableGen/Common/CodeGenTarget.h
+++ b/backend/utils/TableGen/Common/CodeGenTarget.h
@@ -53,6 +53,7 @@ struct NormalizedRegisterClass final {
   std::uint64_t Lanes = 0;
   std::vector<std::uint32_t> Registers;
   std::vector<std::uint32_t> AllocationOrder;
+  std::vector<std::uint32_t> SuperClasses;
   bool Allocatable = true;
   std::uint32_t CopyCost = 1;
 };
-- 
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