From 6c97d54954112be9a5badacaec8efa1d05bd7d15 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 19 Aug 2026 02:50:30 +0800 Subject: [RISCV][GlobalISel] Generate indirect branch selection --- backend/utils/TableGen/RegisterInfoEmitter.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'backend/utils/TableGen/RegisterInfoEmitter.cpp') diff --git a/backend/utils/TableGen/RegisterInfoEmitter.cpp b/backend/utils/TableGen/RegisterInfoEmitter.cpp index a4caa69..0eee15c 100644 --- a/backend/utils/TableGen/RegisterInfoEmitter.cpp +++ b/backend/utils/TableGen/RegisterInfoEmitter.cpp @@ -20,6 +20,15 @@ void emitRegisterIDList(std::ostream &Output, const NormalizedTargetModel &Model Output << "PhysicalRegisterID::" << findRegister(Model, ID).Symbol << ", "; } +void emitRegisterClassIDList(std::ostream &Output, const NormalizedTargetModel &Model, + std::span IDs) { + for (const std::uint32_t ID : IDs) { + const auto Position = + std::ranges::find(Model.RegisterClasses, ID, &NormalizedRegisterClass::ID); + Output << "RegisterClass::" << Position->Symbol << ", "; + } +} + } // namespace [[nodiscard]] std::string emitRegisterHeader(const NormalizedTargetModel &Model, @@ -114,6 +123,8 @@ std::string emitRegisterInfo(const NormalizedTargetModel &Model, std::string_vie emitRegisterIDList(Output, Model, Class.Registers); Output << "}, {"; emitRegisterIDList(Output, Model, Class.AllocationOrder); + Output << "}, {"; + emitRegisterClassIDList(Output, Model, Class.SuperClasses); Output << "}, RegisterBank::" << findRegisterBank(Model, Class.BankID).Symbol << ", " << Class.SizeInBits << ", " << Class.SpillSizeInBits << ", " << Class.SpillAlignmentInBits << ", " << Class.Lanes << ", " -- cgit v1.2.3