From 6c97d54954112be9a5badacaec8efa1d05bd7d15 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Wed, 19 Aug 2026 02:50:30 +0800
Subject: [RISCV][GlobalISel] Generate indirect branch selection

---
 backend/utils/TableGen/Common/CodeGenRegisters.cpp | 16 ++++++++++++++++
 backend/utils/TableGen/Common/CodeGenTarget.h      |  1 +
 backend/utils/TableGen/RegisterInfoEmitter.cpp     | 11 +++++++++++
 3 files changed, 28 insertions(+)

(limited to 'backend/utils')

diff --git a/backend/utils/TableGen/Common/CodeGenRegisters.cpp b/backend/utils/TableGen/Common/CodeGenRegisters.cpp
index 839196e..9fa8d7c 100644
--- a/backend/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/backend/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -132,6 +132,9 @@ namespace rcc::targetgen {
       return false;
     }
     ClassBySymbol.emplace(Class.Symbol, Class.ID);
+  }
+  for (const SourceRegisterClass &Class : Input.RegisterClasses) {
+    const auto Bank = BankBySymbol.find(Class.BankSymbol);
     NormalizedRegisterClass Normalized{
         .ID = Class.ID,
         .Symbol = Class.Symbol,
@@ -143,6 +146,7 @@ namespace rcc::targetgen {
         .Lanes = Class.Lanes,
         .Registers = {},
         .AllocationOrder = {},
+        .SuperClasses = {},
         .Allocatable = Class.Allocatable,
         .CopyCost = Class.CopyCost,
     };
@@ -166,6 +170,18 @@ namespace rcc::targetgen {
       }
       Normalized.AllocationOrder.push_back(Register->second);
     }
+    std::unordered_set<std::uint32_t> SuperClasses;
+    for (const std::string &Symbol : Class.SuperClassSymbols) {
+      const auto SuperClass = ClassBySymbol.find(Symbol);
+      if (SuperClass == ClassBySymbol.end() || SuperClass->second == Class.ID ||
+          !SuperClasses.insert(SuperClass->second).second) {
+        fail(Class.Range,
+             "register class superclasses must reference distinct declared classes other than "
+             "the class itself");
+        return false;
+      }
+      Normalized.SuperClasses.push_back(SuperClass->second);
+    }
     if ((Normalized.Allocatable && Normalized.AllocationOrder.empty()) ||
         (!Normalized.Allocatable && !Normalized.AllocationOrder.empty())) {
       fail(Class.Range, "allocatable register classes require an allocation order and "
diff --git a/backend/utils/TableGen/Common/CodeGenTarget.h b/backend/utils/TableGen/Common/CodeGenTarget.h
index 97e1447..9a7c0a2 100644
--- a/backend/utils/TableGen/Common/CodeGenTarget.h
+++ b/backend/utils/TableGen/Common/CodeGenTarget.h
@@ -53,6 +53,7 @@ struct NormalizedRegisterClass final {
   std::uint64_t Lanes = 0;
   std::vector<std::uint32_t> Registers;
   std::vector<std::uint32_t> AllocationOrder;
+  std::vector<std::uint32_t> SuperClasses;
   bool Allocatable = true;
   std::uint32_t CopyCost = 1;
 };
diff --git a/backend/utils/TableGen/RegisterInfoEmitter.cpp b/backend/utils/TableGen/RegisterInfoEmitter.cpp
index a4caa69..0eee15c 100644
--- a/backend/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/backend/utils/TableGen/RegisterInfoEmitter.cpp
@@ -20,6 +20,15 @@ void emitRegisterIDList(std::ostream &Output, const NormalizedTargetModel &Model
     Output << "PhysicalRegisterID::" << findRegister(Model, ID).Symbol << ", ";
 }
 
+void emitRegisterClassIDList(std::ostream &Output, const NormalizedTargetModel &Model,
+                             std::span<const std::uint32_t> IDs) {
+  for (const std::uint32_t ID : IDs) {
+    const auto Position =
+        std::ranges::find(Model.RegisterClasses, ID, &NormalizedRegisterClass::ID);
+    Output << "RegisterClass::" << Position->Symbol << ", ";
+  }
+}
+
 } // namespace
 
 [[nodiscard]] std::string emitRegisterHeader(const NormalizedTargetModel &Model,
@@ -114,6 +123,8 @@ std::string emitRegisterInfo(const NormalizedTargetModel &Model, std::string_vie
     emitRegisterIDList(Output, Model, Class.Registers);
     Output << "}, {";
     emitRegisterIDList(Output, Model, Class.AllocationOrder);
+    Output << "}, {";
+    emitRegisterClassIDList(Output, Model, Class.SuperClasses);
     Output << "}, RegisterBank::" << findRegisterBank(Model, Class.BankID).Symbol << ", "
            << Class.SizeInBits << ", " << Class.SpillSizeInBits << ", "
            << Class.SpillAlignmentInBits << ", " << Class.Lanes << ", "
-- 
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