From 2fac7e284531dccd9919a3207902e08d4def5cf8 Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Tue, 10 Nov 2026 03:34:30 +0800 Subject: [mubios] Configure PIIX PCI interrupt routing during POST PCI devices retained interrupt line zero, causing e1000 to request the timer IRQ and fail to bring up the network interface. Enumerate the root PCI bus, configure PIIX3 PIRQ A-D to IRQ10/10/11/11, and assign device interrupt lines using the QEMU pc slot and pin mapping. Keep the PIIX PM SCI on IRQ9 and configure level triggering in the ELCR while preserving other IRQ settings. Signed-off-by: Richard Qin --- mubios/core/post.c | 1 + 1 file changed, 1 insertion(+) (limited to 'mubios/core') diff --git a/mubios/core/post.c b/mubios/core/post.c index 8d12369..9a54dd6 100644 --- a/mubios/core/post.c +++ b/mubios/core/post.c @@ -37,6 +37,7 @@ post_main (void) pic_init (); pit_init (); ioapic_init (); + pci_irq_init (); ata_init (); volatile u8 *mbr; -- cgit v1.2.3