From f6441a2e6f901748b504ef93872649c9463a404e Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Sun, 15 Mar 2026 16:07:39 +0800 Subject: initial commit: project architecture --- rv64cpu/docs/isa_support.md | 200 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 rv64cpu/docs/isa_support.md (limited to 'rv64cpu/docs/isa_support.md') diff --git a/rv64cpu/docs/isa_support.md b/rv64cpu/docs/isa_support.md new file mode 100644 index 0000000..e56eac6 --- /dev/null +++ b/rv64cpu/docs/isa_support.md @@ -0,0 +1,200 @@ +# ISA Support Matrix + +## Target ISA String + +``` +RV64GCZicsr_Zifencei +``` + +Equivalent to `RV64IMAFDCZicsr_Zifencei` + +--- + +## Extension Implementation Status + +| Extension | Full Name | Status | Description | +|---|---|---|---| +| **I** | Base Integer (RV64I) | πŸ”΄ Not implemented | 64-bit base integer instruction set | +| **M** | Multiply/Divide | πŸ”΄ Not implemented | Multiply, divide, remainder | +| **A** | Atomic | πŸ”΄ Not implemented | LR/SC, AMO atomic instructions | +| **F** | Single-Precision Float | πŸ”΄ Not implemented | 32-bit IEEE 754 floating-point | +| **D** | Double-Precision Float | πŸ”΄ Not implemented | 64-bit IEEE 754 floating-point | +| **C** | Compressed | πŸ”΄ Not implemented | 16-bit compressed instructions | +| **Zicsr** | CSR Instructions | πŸ”΄ Not implemented | CSRRW/CSRRS/CSRRC/CSRRWI/CSRRSI/CSRRCI | +| **Zifencei** | Instruction Fence | πŸ”΄ Not implemented | FENCE.I instruction | + +--- + +## RV64I Instruction List + +### R-type Arithmetic/Logic +| Instruction | Operation | Status | +|---|---|---| +| ADD | rd = rs1 + rs2 | ⬜ | +| SUB | rd = rs1 - rs2 | ⬜ | +| AND | rd = rs1 & rs2 | ⬜ | +| OR | rd = rs1 \| rs2 | ⬜ | +| XOR | rd = rs1 ^ rs2 | ⬜ | +| SLL | rd = rs1 << rs2[5:0] | ⬜ | +| SRL | rd = rs1 >> rs2[5:0] (logical) | ⬜ | +| SRA | rd = rs1 >> rs2[5:0] (arith) | ⬜ | +| SLT | rd = (rs1 < rs2) ? 1 : 0 (signed) | ⬜ | +| SLTU | rd = (rs1 < rs2) ? 1 : 0 (unsigned) | ⬜ | + +### R-type RV64 Word Operations +| Instruction | Operation | Status | +|---|---|---| +| ADDW | rd = sext((rs1+rs2)[31:0]) | ⬜ | +| SUBW | rd = sext((rs1-rs2)[31:0]) | ⬜ | +| SLLW | rd = sext((rs1 << rs2[4:0])[31:0]) | ⬜ | +| SRLW | rd = sext((rs1[31:0] >> rs2[4:0])) | ⬜ | +| SRAW | rd = sext((rs1[31:0] >>> rs2[4:0])) | ⬜ | + +### I-type Immediate Arithmetic +| Instruction | Operation | Status | +|---|---|---| +| ADDI | rd = rs1 + imm | ⬜ | +| ANDI | rd = rs1 & imm | ⬜ | +| ORI | rd = rs1 \| imm | ⬜ | +| XORI | rd = rs1 ^ imm | ⬜ | +| SLLI | rd = rs1 << shamt[5:0] | ⬜ | +| SRLI | rd = rs1 >> shamt[5:0] (logical) | ⬜ | +| SRAI | rd = rs1 >> shamt[5:0] (arith) | ⬜ | +| SLTI | rd = (rs1 < imm) ? 1 : 0 (signed) | ⬜ | +| SLTIU | rd = (rs1 < imm) ? 1 : 0 (unsigned) | ⬜ | +| ADDIW | rd = sext((rs1+imm)[31:0]) | ⬜ | +| SLLIW | rd = sext((rs1 << shamt[4:0])[31:0]) | ⬜ | +| SRLIW | rd = sext((rs1[31:0] >> shamt[4:0])) | ⬜ | +| SRAIW | rd = sext((rs1[31:0] >>> shamt[4:0])) | ⬜ | + +### Load +| Instruction | Width | Sign Extension | Status | +|---|---|---|---| +| LB | 8-bit | Signed | ⬜ | +| LBU | 8-bit | Zero-extended | ⬜ | +| LH | 16-bit | Signed | ⬜ | +| LHU | 16-bit | Zero-extended | ⬜ | +| LW | 32-bit | Signed | ⬜ | +| LWU | 32-bit | Zero-extended | ⬜ | +| LD | 64-bit | β€” | ⬜ | + +### Store +| Instruction | Width | Status | +|---|---|---| +| SB | 8-bit | ⬜ | +| SH | 16-bit | ⬜ | +| SW | 32-bit | ⬜ | +| SD | 64-bit | ⬜ | + +### Branch +| Instruction | Condition | Status | +|---|---|---| +| BEQ | rs1 == rs2 | ⬜ | +| BNE | rs1 != rs2 | ⬜ | +| BLT | rs1 < rs2 (signed) | ⬜ | +| BGE | rs1 >= rs2 (signed) | ⬜ | +| BLTU | rs1 < rs2 (unsigned) | ⬜ | +| BGEU | rs1 >= rs2 (unsigned) | ⬜ | + +### Upper Immediate / Jump +| Instruction | Operation | Status | +|---|---|---| +| LUI | rd = imm << 12 | ⬜ | +| AUIPC | rd = pc + (imm << 12) | ⬜ | +| JAL | rd = pc+4; pc = pc + imm | ⬜ | +| JALR | rd = pc+4; pc = (rs1 + imm) & ~1 | ⬜ | + +### System +| Instruction | Status | +|---|---| +| ECALL | ⬜ | +| EBREAK | ⬜ | +| MRET | ⬜ | +| SRET | ⬜ | +| WFI | ⬜ | +| FENCE | ⬜ | +| FENCE.I | ⬜ | +| SFENCE.VMA | ⬜ | + +--- + +## M Extension (Multiply/Divide) + +| Instruction | Operation | Status | +|---|---|---| +| MUL | rd = (rs1 Γ— rs2)[63:0] | ⬜ | +| MULH | rd = (rs1 Γ— rs2)[127:64] signed | ⬜ | +| MULHSU | rd = (rs1 Γ— rs2)[127:64] signedΓ—unsigned | ⬜ | +| MULHU | rd = (rs1 Γ— rs2)[127:64] unsigned | ⬜ | +| DIV | rd = rs1 / rs2 signed | ⬜ | +| DIVU | rd = rs1 / rs2 unsigned | ⬜ | +| REM | rd = rs1 % rs2 signed | ⬜ | +| REMU | rd = rs1 % rs2 unsigned | ⬜ | +| MULW | rd = sext((rs1Γ—rs2)[31:0]) | ⬜ | +| DIVW / DIVUW | 32-bit division | ⬜ | +| REMW / REMUW | 32-bit remainder | ⬜ | + +--- + +## A Extension (Atomic Instructions) + +| Instruction | Status | +|---|---| +| LR.W / LR.D | ⬜ | +| SC.W / SC.D | ⬜ | +| AMOSWAP.W/D | ⬜ | +| AMOADD.W/D | ⬜ | +| AMOAND.W/D | ⬜ | +| AMOOR.W/D | ⬜ | +| AMOXOR.W/D | ⬜ | +| AMOMAX[U].W/D | ⬜ | +| AMOMIN[U].W/D | ⬜ | + +--- + +## F/D Extension (Floating-Point) + +| Category | F (32-bit) Instructions | D (64-bit) Instructions | Status | +|---|---|---|---| +| Load/Store | FLW, FSW | FLD, FSD | ⬜ | +| Arithmetic | FADD.S, FSUB.S, FMUL.S, FDIV.S, FSQRT.S | FADD.D, ... | ⬜ | +| Fused Multiply-Add | FMADD.S, FMSUB.S, FNMADD.S, FNMSUB.S | FMADD.D, ... | ⬜ | +| Sign Manipulation | FSGNJ[N/X].S | FSGNJ[N/X].D | ⬜ | +| Compare | FEQ.S, FLT.S, FLE.S | FEQ.D, FLT.D, FLE.D | ⬜ | +| Classify | FCLASS.S | FCLASS.D | ⬜ | +| Conversion | FCVT.W/WU/L/LU.S, FCVT.S.W/WU/L/LU | FCVT.*.D | ⬜ | +| F↔D Conversion | β€” | FCVT.S.D, FCVT.D.S | ⬜ | +| Move | FMV.X.W, FMV.W.X | FMV.X.D, FMV.D.X | ⬜ | +| MIN/MAX | FMIN.S, FMAX.S | FMIN.D, FMAX.D | ⬜ | + +### Floating-Point CSRs +| CSR | Address | Description | +|---|---|---| +| `fflags` | 0x001 | Floating-point exception flags (NV, DZ, OF, UF, NX) | +| `frm` | 0x002 | Floating-point rounding mode | +| `fcsr` | 0x003 | fflags + frm combined | + +--- + +## C Extension (Compressed Instructions) + +16-bit encoded subset of common instructions, improving code density. Requires handling 16/32-bit mixed instruction stream alignment at the IF stage. + +| Quadrant | Selected Instructions | Status | +|---|---|---| +| C0 | C.LW, C.LD, C.SW, C.SD, C.ADDI4SPN | ⬜ | +| C1 | C.ADDI, C.LI, C.LUI, C.SRLI, C.SRAI, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.J, C.BEQZ, C.BNEZ | ⬜ | +| C2 | C.SLLI, C.LDSP, C.LWSP, C.JR, C.MV, C.JALR, C.ADD, C.SDSP, C.SWSP | ⬜ | + +--- + +## Zicsr Instructions + +| Instruction | Operation | Status | +|---|---|---| +| CSRRW | t=CSR; CSR=rs1; rd=t | ⬜ | +| CSRRS | t=CSR; CSR=t\|rs1; rd=t | ⬜ | +| CSRRC | t=CSR; CSR=t&~rs1; rd=t | ⬜ | +| CSRRWI | t=CSR; CSR=zimm; rd=t | ⬜ | +| CSRRSI | t=CSR; CSR=t\|zimm; rd=t | ⬜ | +| CSRRCI | t=CSR; CSR=t&~zimm; rd=t | ⬜ | -- cgit v1.2.3 From a03760a54a0f0f0de1c75f449427554674aabaaa Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Thu, 19 Mar 2026 02:25:41 +0800 Subject: Update the latest progress --- rv64cpu/docs/isa_support.md | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'rv64cpu/docs/isa_support.md') diff --git a/rv64cpu/docs/isa_support.md b/rv64cpu/docs/isa_support.md index e56eac6..cf8c9c4 100644 --- a/rv64cpu/docs/isa_support.md +++ b/rv64cpu/docs/isa_support.md @@ -14,14 +14,22 @@ Equivalent to `RV64IMAFDCZicsr_Zifencei` | Extension | Full Name | Status | Description | |---|---|---|---| -| **I** | Base Integer (RV64I) | πŸ”΄ Not implemented | 64-bit base integer instruction set | +| **I** | Base Integer (RV64I) | 🟑 In progress | Five-stage RV64I pipeline, ALU, and branch unit implemented and covered by unit tests ([rtl/core/alu.sv](rtl/core/alu.sv), [tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)) | | **M** | Multiply/Divide | πŸ”΄ Not implemented | Multiply, divide, remainder | | **A** | Atomic | πŸ”΄ Not implemented | LR/SC, AMO atomic instructions | | **F** | Single-Precision Float | πŸ”΄ Not implemented | 32-bit IEEE 754 floating-point | | **D** | Double-Precision Float | πŸ”΄ Not implemented | 64-bit IEEE 754 floating-point | | **C** | Compressed | πŸ”΄ Not implemented | 16-bit compressed instructions | -| **Zicsr** | CSR Instructions | πŸ”΄ Not implemented | CSRRW/CSRRS/CSRRC/CSRRWI/CSRRSI/CSRRCI | -| **Zifencei** | Instruction Fence | πŸ”΄ Not implemented | FENCE.I instruction | +| **Zicsr** | CSR Instructions | 🟒 Implemented | Full CSR unit with delegation, FCSR, and dedicated testbench ([rtl/core/csr_unit.sv](rtl/core/csr_unit.sv), [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc)) | +| **Zifencei** | Instruction Fence | 🟑 Decoding only | Decoder recognizes FENCE.I; cache invalidation hookup pending | + +--- + +## Recent Progress Highlights (2026-03) + +- **CSR subsystem**: `csr_unit` now handles delegation, privilege transitions, and floating-point CSRs, verified by [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc). +- **Integer execution path**: ALU, branch, and decode paths for RV64I arithmetic/logic instructions are implemented with passing unit tests ([tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)). +- **Decoder coverage**: Load/store, immediate, and system opcode paths exist with clear TODO markers for upcoming M/A/F extensions, see [rtl/core/decoder.sv](rtl/core/decoder.sv). --- -- cgit v1.2.3 From def178f9df3819f01092400893651a148d529f2f Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Wed, 1 Apr 2026 05:11:48 +0800 Subject: docs: update README and ISA support matrix with new dependencies and compliance status --- rv64cpu/README.md | 27 ++++++++++++++++++++++----- rv64cpu/docs/isa_support.md | 40 ++++++++++++++++++++++++++++------------ 2 files changed, 50 insertions(+), 17 deletions(-) (limited to 'rv64cpu/docs/isa_support.md') diff --git a/rv64cpu/README.md b/rv64cpu/README.md index e2b767d..72b3546 100644 --- a/rv64cpu/README.md +++ b/rv64cpu/README.md @@ -24,6 +24,9 @@ Written in SystemVerilog, simulated with Verilator, targeting official riscv-arc - CMake β‰₯ 3.20 - C++17 compiler (GCC / Clang) - [riscv64-unknown-elf-gcc](https://github.com/riscv-collab/riscv-gnu-toolchain) (software compilation, optional) +- [uv](https://docs.astral.sh/uv/) (ACT4 Python tooling) +- [podman](https://podman.io/) (riscv-unified-db runtime) +- [sail_riscv_sim 0.10](https://github.com/riscv/sail-riscv/releases/tag/0.10) (reference model for ACT4) - [GTKWave](http://gtkwave.sourceforge.net/) (waveform viewer, optional) ### Build Simulation @@ -54,10 +57,24 @@ cmake --build build_sw -j$(nproc) # Initialize riscv-arch-test submodule git submodule update --init --recursive -# Run RV64I test suite -python3 scripts/run_compliance.py --suite rv64i -v +# Sync ACT4 python dependencies +cd sw/riscv-arch-test && uv sync --frozen && cd ../.. + +# Run strict full implemented suite (reference signature compare enabled) +python3 scripts/run_compliance.py --suite rv64full --max-cycles 200000 --require-reference ``` +Verified strict suites (all pass): + +- `rv64i` +- `rv64im` +- `rv64ia` +- `rv64ic` +- `rv64if` +- `rv64id` +- `rv64priv` +- `rv64full` (aggregate) + ### View Waveforms ```bash @@ -111,12 +128,12 @@ richard-cpu/ | Phase | Milestone | |---|---| -| P1 | RV64I five-stage pipeline + hazard handling | -| P2 | CSR + M/S/U privilege levels + Trap | +| P1 | RV64I five-stage pipeline + hazard handling (Done) | +| P2 | CSR + M/S/U privilege levels + Trap (Done) | | P3 | MMU (Sv39 TLB + PTW) | | P4 | Cache + AXI4-Full Burst | | P5 | Peripherals + AXI4-Lite bridge + SoC integration | -| P6 | Pass riscv-arch-test | +| P6 | Pass riscv-arch-test (In Progress: strict suites above all pass) | | P7 | M/F/D/A/C extensions + FPGA bring-up | ## License diff --git a/rv64cpu/docs/isa_support.md b/rv64cpu/docs/isa_support.md index cf8c9c4..0173a58 100644 --- a/rv64cpu/docs/isa_support.md +++ b/rv64cpu/docs/isa_support.md @@ -14,22 +14,38 @@ Equivalent to `RV64IMAFDCZicsr_Zifencei` | Extension | Full Name | Status | Description | |---|---|---|---| -| **I** | Base Integer (RV64I) | 🟑 In progress | Five-stage RV64I pipeline, ALU, and branch unit implemented and covered by unit tests ([rtl/core/alu.sv](rtl/core/alu.sv), [tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)) | -| **M** | Multiply/Divide | πŸ”΄ Not implemented | Multiply, divide, remainder | -| **A** | Atomic | πŸ”΄ Not implemented | LR/SC, AMO atomic instructions | -| **F** | Single-Precision Float | πŸ”΄ Not implemented | 32-bit IEEE 754 floating-point | -| **D** | Double-Precision Float | πŸ”΄ Not implemented | 64-bit IEEE 754 floating-point | -| **C** | Compressed | πŸ”΄ Not implemented | 16-bit compressed instructions | +| **I** | Base Integer (RV64I) | 🟒 Implemented | Strict ACT4 compliance suite passes (`rv64i`) | +| **M** | Multiply/Divide | 🟒 Implemented | Strict ACT4 compliance suite passes (`rv64im`) | +| **A** | Atomic | 🟒 Implemented | Strict ACT4 compliance suite passes (`rv64ia`) | +| **F** | Single-Precision Float | 🟒 Implemented | Strict ACT4 compliance suite passes (`rv64if`) | +| **D** | Double-Precision Float | 🟒 Implemented | Strict ACT4 compliance suite passes (`rv64id`) | +| **C** | Compressed | 🟒 Implemented | Strict ACT4 compliance suite passes (`rv64ic`) | | **Zicsr** | CSR Instructions | 🟒 Implemented | Full CSR unit with delegation, FCSR, and dedicated testbench ([rtl/core/csr_unit.sv](rtl/core/csr_unit.sv), [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc)) | -| **Zifencei** | Instruction Fence | 🟑 Decoding only | Decoder recognizes FENCE.I; cache invalidation hookup pending | +| **Zifencei** | Instruction Fence | 🟒 Implemented | Included in strict ACT4 passing suites | ---- +Privilege-related tests (`S`, `Sm`) also pass through `rv64priv` strict suite. -## Recent Progress Highlights (2026-03) +--- -- **CSR subsystem**: `csr_unit` now handles delegation, privilege transitions, and floating-point CSRs, verified by [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc). -- **Integer execution path**: ALU, branch, and decode paths for RV64I arithmetic/logic instructions are implemented with passing unit tests ([tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)). -- **Decoder coverage**: Load/store, immediate, and system opcode paths exist with clear TODO markers for upcoming M/A/F extensions, see [rtl/core/decoder.sv](rtl/core/decoder.sv). +## Recent Progress Highlights (2026-04) + +- `riscv-arch-test` ACT4 flow integrated in `scripts/run_compliance.py`. +- Dedicated `tb/compliance/compliance_runner.cc` executes ELF tests and dumps signatures. +- Strict suite passes with reference comparison enabled (`--require-reference`): + - `rv64i` (51/51) + - `rv64im` (64/64) + - `rv64ia` (51/51) + - `rv64ic` (51/51) + - `rv64if` (133/133) + - `rv64id` (165/165) + - `rv64priv` (2/2) + - `rv64full` aggregate (262/262) + +## Detailed Instruction Tables + +The detailed per-instruction checklist sections below are retained as reference, +but are not the primary source of truth for completion status at this stage. +Current completion is determined by strict ACT4 suite pass results listed above. --- -- cgit v1.2.3