From abddef6c366a4a8e8f878158cf1bac14f9ad59b2 Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Tue, 17 Mar 2026 16:51:29 +0000 Subject: docs: Finalized Richard CPU RTL architectural and naming convention audit report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com> --- rv64cpu/rtl/core/decoder.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'rv64cpu/rtl/core/decoder.sv') diff --git a/rv64cpu/rtl/core/decoder.sv b/rv64cpu/rtl/core/decoder.sv index 585a018..c948646 100644 --- a/rv64cpu/rtl/core/decoder.sv +++ b/rv64cpu/rtl/core/decoder.sv @@ -80,7 +80,7 @@ module decoder assign opcode = instr[6:0]; assign rd_addr = instr[11:7]; assign funct3 = instr[14:12]; - assign rs1_addr = instr[19:15]; + assign rs1_addr = (opcode == OPCODE_LUI) ? 5'b00000 : instr[19:15]; assign rs2_addr = instr[24:20]; assign funct7 = instr[31:25]; -- cgit v1.2.3