From abddef6c366a4a8e8f878158cf1bac14f9ad59b2 Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Tue, 17 Mar 2026 16:51:29 +0000 Subject: docs: Finalized Richard CPU RTL architectural and naming convention audit report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com> --- rv64cpu/rtl/core/id_ex_reg.sv | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) (limited to 'rv64cpu/rtl/core/id_ex_reg.sv') diff --git a/rv64cpu/rtl/core/id_ex_reg.sv b/rv64cpu/rtl/core/id_ex_reg.sv index b8a3bd7..e88ce17 100644 --- a/rv64cpu/rtl/core/id_ex_reg.sv +++ b/rv64cpu/rtl/core/id_ex_reg.sv @@ -36,6 +36,8 @@ module id_ex_reg input logic [XLEN-1:0] id_pc, input logic [XLEN-1:0] id_rs1_rdata, input logic [XLEN-1:0] id_rs2_rdata, + input logic [4:0] id_rs1_addr, + input logic [4:0] id_rs2_addr, input logic [XLEN-1:0] id_imm, // Execution Control @@ -75,6 +77,8 @@ module id_ex_reg output logic [XLEN-1:0] ex_pc, output logic [XLEN-1:0] ex_rs1_rdata, output logic [XLEN-1:0] ex_rs2_rdata, + output logic [4:0] ex_rs1_addr, + output logic [4:0] ex_rs2_addr, output logic [XLEN-1:0] ex_imm, // Execution Control @@ -109,10 +113,12 @@ module id_ex_reg ); always_ff @(posedge clk) begin - if (rst || flush_en) begin + if (rst) begin ex_pc <= '0; ex_rs1_rdata <= '0; ex_rs2_rdata <= '0; + ex_rs1_addr <= '0; + ex_rs2_addr <= '0; ex_imm <= '0; ex_alu_op <= ALU_ADD; // NOP is effectively ADD x0, x0, 0 ex_alu_src1_sel <= '0; @@ -138,10 +144,37 @@ module id_ex_reg ex_is_sfence_vma <= '0; ex_is_fence <= '0; ex_is_fence_i <= '0; + end else if (flush_en) begin + ex_alu_op <= ALU_ADD; // NOP is effectively ADD x0, x0, 0 + ex_alu_src1_sel <= '0; + ex_alu_src2_sel <= '0; + ex_is_word_op <= '0; + ex_is_branch <= '0; + ex_branch_op <= BRANCH_EQ; + ex_is_jump <= '0; + ex_is_load <= '0; + ex_is_store <= '0; + ex_mem_size <= '0; + ex_reg_write_en <= '0; // VERY IMPORTANT: Do not write to regfile on NOP + ex_rd_addr <= '0; + ex_wb_sel <= '0; + ex_is_csr <= '0; + ex_csr_op <= '0; + ex_illegal_instr <= '0; + ex_is_ecall <= '0; + ex_is_ebreak <= '0; + ex_is_mret <= '0; + ex_is_sret <= '0; + ex_is_wfi <= '0; + ex_is_sfence_vma <= '0; + ex_is_fence <= '0; + ex_is_fence_i <= '0; end else if (~stall_en) begin ex_pc <= id_pc; ex_rs1_rdata <= id_rs1_rdata; ex_rs2_rdata <= id_rs2_rdata; + ex_rs1_addr <= id_rs1_addr; + ex_rs2_addr <= id_rs2_addr; ex_imm <= id_imm; ex_alu_op <= id_alu_op; ex_alu_src1_sel <= id_alu_src1_sel; -- cgit v1.2.3