From cf0476e565c74082f011a6c428095e60a743b822 Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Wed, 1 Apr 2026 00:58:22 +0800 Subject: feat: Complete CSR/privileged/exception interrupt path and fill in strict acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22) --- rv64cpu/rtl/core/id_ex_reg.sv | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'rv64cpu/rtl/core/id_ex_reg.sv') diff --git a/rv64cpu/rtl/core/id_ex_reg.sv b/rv64cpu/rtl/core/id_ex_reg.sv index e88ce17..9375bb4 100644 --- a/rv64cpu/rtl/core/id_ex_reg.sv +++ b/rv64cpu/rtl/core/id_ex_reg.sv @@ -32,6 +32,9 @@ module id_ex_reg // Inputs from ID Stage + // Instruction payload + input logic [INST_WIDTH-1:0] id_instr, + // Data/Operands input logic [XLEN-1:0] id_pc, input logic [XLEN-1:0] id_rs1_rdata, @@ -73,6 +76,9 @@ module id_ex_reg // Outputs to EX Stage + // Instruction payload + output logic [INST_WIDTH-1:0] ex_instr, + // Data/Operands output logic [XLEN-1:0] ex_pc, output logic [XLEN-1:0] ex_rs1_rdata, @@ -114,6 +120,7 @@ module id_ex_reg always_ff @(posedge clk) begin if (rst) begin + ex_instr <= '0; ex_pc <= '0; ex_rs1_rdata <= '0; ex_rs2_rdata <= '0; @@ -145,6 +152,7 @@ module id_ex_reg ex_is_fence <= '0; ex_is_fence_i <= '0; end else if (flush_en) begin + ex_instr <= '0; ex_alu_op <= ALU_ADD; // NOP is effectively ADD x0, x0, 0 ex_alu_src1_sel <= '0; ex_alu_src2_sel <= '0; @@ -170,6 +178,7 @@ module id_ex_reg ex_is_fence <= '0; ex_is_fence_i <= '0; end else if (~stall_en) begin + ex_instr <= id_instr; ex_pc <= id_pc; ex_rs1_rdata <= id_rs1_rdata; ex_rs2_rdata <= id_rs2_rdata; -- cgit v1.2.3