From 6f57dd79572c177b775a934bee54ceb85a55c28a Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Sat, 7 Nov 2026 03:14:46 +0800 Subject: refactor: rename RTL source files --- rv64cpu/rtl/core/mmu/mmu.sv | 359 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 359 insertions(+) create mode 100644 rv64cpu/rtl/core/mmu/mmu.sv (limited to 'rv64cpu/rtl/core/mmu/mmu.sv') diff --git a/rv64cpu/rtl/core/mmu/mmu.sv b/rv64cpu/rtl/core/mmu/mmu.sv new file mode 100644 index 0000000..169bf81 --- /dev/null +++ b/rv64cpu/rtl/core/mmu/mmu.sv @@ -0,0 +1,359 @@ +// Richard CPU +// Copyright (C) 2026 Richard Qin + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// File path: rtl/core/mmu/mmu_top.sv +// Description: MMU top-level integrating iTLB + dTLB + shared PTW + +module mmu_top + import rv64_pkg::*; +#( + parameter int ITLB_ENTRIES = 16, + parameter int DTLB_ENTRIES = 32, + parameter int ASID_WIDTH = 16 +)( + input logic clk, + input logic rst, + + // CSR/context inputs + input logic [XLEN-1:0] satp_value, + input logic [1:0] priv_mode, + input logic sum, + input logic mxr, + + // i-side translation request + input logic i_req_valid, + output logic i_req_ready, + input logic [XLEN-1:0] i_req_vaddr, + output logic i_resp_valid, + output logic i_resp_hit, + output logic i_resp_page_fault, + output logic [XLEN-1:0] i_resp_vaddr, + output logic [XLEN-1:0] i_resp_paddr, + + // d-side translation request + input logic d_req_valid, + output logic d_req_ready, + input logic [XLEN-1:0] d_req_vaddr, + input logic d_req_is_store, + output logic d_resp_valid, + output logic d_resp_hit, + output logic d_resp_page_fault, + output logic [XLEN-1:0] d_resp_paddr, + + // sfence / invalidation + input logic flush_all, + input logic flush_asid_valid, + input logic [ASID_WIDTH-1:0] flush_asid, + input logic flush_vpn_valid, + input logic [44:0] flush_vpn, + + // PTW memory interface + output logic ptw_mem_req_valid, + input logic ptw_mem_req_ready, + output logic [XLEN-1:0] ptw_mem_req_addr, + input logic ptw_mem_resp_valid, + input logic [XLEN-1:0] ptw_mem_resp_data +); + + localparam logic [3:0] SATP_MODE_BARE = 4'd0; + + typedef enum logic [0:0] { + PTW_SRC_I = 1'b0, + PTW_SRC_D = 1'b1 + } ptw_src_t; + + logic [ASID_WIDTH-1:0] req_asid; + logic [3:0] req_mode; + + logic i_tlb_resp_valid; + logic i_tlb_resp_hit; + logic [XLEN-1:0] i_tlb_resp_paddr; + logic i_tlb_resp_page_fault; + logic i_tlb_resp_need_ptw; + + logic d_tlb_resp_valid; + logic d_tlb_resp_hit; + logic [XLEN-1:0] d_tlb_resp_paddr; + logic d_tlb_resp_page_fault; + logic d_tlb_resp_need_ptw; + + logic i_pending_q; + logic d_pending_q; + logic [XLEN-1:0] i_pending_vaddr_q; + logic [XLEN-1:0] d_pending_vaddr_q; + logic [1:0] i_pending_priv_q; + logic [1:0] d_pending_priv_q; + logic i_pending_sum_q; + logic d_pending_sum_q; + logic i_pending_mxr_q; + logic d_pending_mxr_q; + logic [ASID_WIDTH-1:0] i_pending_asid_q; + logic [ASID_WIDTH-1:0] d_pending_asid_q; + logic [3:0] i_pending_mode_q; + logic [3:0] d_pending_mode_q; + logic d_pending_is_store_q; + + logic ptw_req_valid; + logic ptw_req_ready; + logic ptw_resp_valid; + logic ptw_resp_fault; + logic [XLEN-1:0] ptw_resp_paddr; + + logic ptw_refill_valid; + logic [44:0] ptw_refill_vpn; + logic [43:0] ptw_refill_ppn; + logic [2:0] ptw_refill_level; + logic [3:0] ptw_refill_mode; + logic [ASID_WIDTH-1:0] ptw_refill_asid; + logic ptw_refill_g; + logic ptw_refill_u; + logic ptw_refill_r; + logic ptw_refill_w; + logic ptw_refill_x; + logic ptw_refill_a; + logic ptw_refill_d; + + logic ptw_busy_q; + ptw_src_t ptw_owner_q; + ptw_src_t ptw_owner_next; + + logic i_accept; + logic d_accept; + logic i_fast_resp_valid; + logic d_fast_resp_valid; + logic i_ptw_resp_sel; + logic d_ptw_resp_sel; + + logic i_refill_valid; + logic d_refill_valid; + + assign req_mode = satp_value[63:60]; + assign req_asid = satp_value[59 -: ASID_WIDTH]; + + assign i_req_ready = !i_pending_q; + assign d_req_ready = !d_pending_q; + assign i_accept = i_req_valid && i_req_ready; + assign d_accept = d_req_valid && d_req_ready; + + assign i_fast_resp_valid = i_accept && (i_tlb_resp_hit || i_tlb_resp_page_fault); + assign d_fast_resp_valid = d_accept && (d_tlb_resp_hit || d_tlb_resp_page_fault); + + assign i_ptw_resp_sel = ptw_resp_valid && (ptw_owner_q == PTW_SRC_I); + assign d_ptw_resp_sel = ptw_resp_valid && (ptw_owner_q == PTW_SRC_D); + + assign i_resp_valid = i_fast_resp_valid || i_ptw_resp_sel; + assign i_resp_hit = i_fast_resp_valid ? i_tlb_resp_hit : (i_ptw_resp_sel && !ptw_resp_fault); + assign i_resp_page_fault = i_fast_resp_valid ? i_tlb_resp_page_fault : (i_ptw_resp_sel && ptw_resp_fault); + assign i_resp_vaddr = i_fast_resp_valid ? i_req_vaddr : i_pending_vaddr_q; + assign i_resp_paddr = i_fast_resp_valid ? i_tlb_resp_paddr : ptw_resp_paddr; + + assign d_resp_valid = d_fast_resp_valid || d_ptw_resp_sel; + assign d_resp_hit = d_fast_resp_valid ? d_tlb_resp_hit : (d_ptw_resp_sel && !ptw_resp_fault); + assign d_resp_page_fault = d_fast_resp_valid ? d_tlb_resp_page_fault : (d_ptw_resp_sel && ptw_resp_fault); + assign d_resp_paddr = d_fast_resp_valid ? d_tlb_resp_paddr : ptw_resp_paddr; + + always_comb begin + if (d_pending_q) begin + ptw_owner_next = PTW_SRC_D; + end else begin + ptw_owner_next = PTW_SRC_I; + end + end + + assign ptw_req_valid = !ptw_busy_q && (d_pending_q || i_pending_q); + + assign i_refill_valid = ptw_refill_valid && (ptw_owner_q == PTW_SRC_I); + assign d_refill_valid = ptw_refill_valid && (ptw_owner_q == PTW_SRC_D); + + always_ff @(posedge clk) begin + if (rst) begin + i_pending_q <= 1'b0; + d_pending_q <= 1'b0; + ptw_busy_q <= 1'b0; + ptw_owner_q <= PTW_SRC_I; + i_pending_vaddr_q <= '0; + d_pending_vaddr_q <= '0; + i_pending_priv_q <= '0; + d_pending_priv_q <= '0; + i_pending_sum_q <= 1'b0; + d_pending_sum_q <= 1'b0; + i_pending_mxr_q <= 1'b0; + d_pending_mxr_q <= 1'b0; + i_pending_asid_q <= '0; + d_pending_asid_q <= '0; + i_pending_mode_q <= SATP_MODE_BARE; + d_pending_mode_q <= SATP_MODE_BARE; + d_pending_is_store_q <= 1'b0; + end else begin + if (i_accept && i_tlb_resp_need_ptw) begin + i_pending_q <= 1'b1; + i_pending_vaddr_q <= i_req_vaddr; + i_pending_priv_q <= priv_mode; + i_pending_sum_q <= sum; + i_pending_mxr_q <= mxr; + i_pending_asid_q <= req_asid; + i_pending_mode_q <= req_mode; + end + + if (d_accept && d_tlb_resp_need_ptw) begin + d_pending_q <= 1'b1; + d_pending_vaddr_q <= d_req_vaddr; + d_pending_priv_q <= priv_mode; + d_pending_sum_q <= sum; + d_pending_mxr_q <= mxr; + d_pending_asid_q <= req_asid; + d_pending_mode_q <= req_mode; + d_pending_is_store_q <= d_req_is_store; + end + + if (ptw_req_valid && ptw_req_ready) begin + ptw_busy_q <= 1'b1; + ptw_owner_q <= ptw_owner_next; + end + + if (ptw_resp_valid) begin + ptw_busy_q <= 1'b0; + if (ptw_owner_q == PTW_SRC_I) begin + i_pending_q <= 1'b0; + end else begin + d_pending_q <= 1'b0; + end + end + end + end + + tlb #( + .ENTRIES(ITLB_ENTRIES), + .ASID_WIDTH(ASID_WIDTH) + ) u_itlb ( + .clk (clk), + .rst (rst), + .req_valid (i_accept), + .req_vaddr (i_req_vaddr), + .req_asid (req_asid), + .req_mode (req_mode), + .req_priv (priv_mode), + .req_is_fetch (1'b1), + .req_is_store (1'b0), + .req_sum (sum), + .req_mxr (mxr), + .resp_valid (i_tlb_resp_valid), + .resp_hit (i_tlb_resp_hit), + .resp_paddr (i_tlb_resp_paddr), + .resp_page_fault (i_tlb_resp_page_fault), + .resp_need_ptw (i_tlb_resp_need_ptw), + .refill_valid (i_refill_valid), + .refill_vpn (ptw_refill_vpn), + .refill_ppn (ptw_refill_ppn), + .refill_level (ptw_refill_level), + .refill_mode (ptw_refill_mode), + .refill_asid (ptw_refill_asid), + .refill_g (ptw_refill_g), + .refill_u (ptw_refill_u), + .refill_r (ptw_refill_r), + .refill_w (ptw_refill_w), + .refill_x (ptw_refill_x), + .refill_a (ptw_refill_a), + .refill_d (ptw_refill_d), + .flush_all (flush_all), + .flush_asid_valid (flush_asid_valid), + .flush_asid (flush_asid), + .flush_vpn_valid (flush_vpn_valid), + .flush_vpn (flush_vpn), + .flush_mode (req_mode) + ); + + tlb #( + .ENTRIES(DTLB_ENTRIES), + .ASID_WIDTH(ASID_WIDTH) + ) u_dtlb ( + .clk (clk), + .rst (rst), + .req_valid (d_accept), + .req_vaddr (d_req_vaddr), + .req_asid (req_asid), + .req_mode (req_mode), + .req_priv (priv_mode), + .req_is_fetch (1'b0), + .req_is_store (d_req_is_store), + .req_sum (sum), + .req_mxr (mxr), + .resp_valid (d_tlb_resp_valid), + .resp_hit (d_tlb_resp_hit), + .resp_paddr (d_tlb_resp_paddr), + .resp_page_fault (d_tlb_resp_page_fault), + .resp_need_ptw (d_tlb_resp_need_ptw), + .refill_valid (d_refill_valid), + .refill_vpn (ptw_refill_vpn), + .refill_ppn (ptw_refill_ppn), + .refill_level (ptw_refill_level), + .refill_mode (ptw_refill_mode), + .refill_asid (ptw_refill_asid), + .refill_g (ptw_refill_g), + .refill_u (ptw_refill_u), + .refill_r (ptw_refill_r), + .refill_w (ptw_refill_w), + .refill_x (ptw_refill_x), + .refill_a (ptw_refill_a), + .refill_d (ptw_refill_d), + .flush_all (flush_all), + .flush_asid_valid (flush_asid_valid), + .flush_asid (flush_asid), + .flush_vpn_valid (flush_vpn_valid), + .flush_vpn (flush_vpn), + .flush_mode (req_mode) + ); + + ptw #( + .ASID_WIDTH(ASID_WIDTH) + ) u_ptw ( + .clk (clk), + .rst (rst), + .req_valid (ptw_req_valid), + .req_ready (ptw_req_ready), + .req_vaddr ((ptw_owner_next == PTW_SRC_D) ? d_pending_vaddr_q : i_pending_vaddr_q), + .req_asid ((ptw_owner_next == PTW_SRC_D) ? d_pending_asid_q : i_pending_asid_q), + .req_mode ((ptw_owner_next == PTW_SRC_D) ? d_pending_mode_q : i_pending_mode_q), + .req_priv ((ptw_owner_next == PTW_SRC_D) ? d_pending_priv_q : i_pending_priv_q), + .req_is_fetch (ptw_owner_next == PTW_SRC_I), + .req_is_store ((ptw_owner_next == PTW_SRC_D) ? d_pending_is_store_q : 1'b0), + .req_sum ((ptw_owner_next == PTW_SRC_D) ? d_pending_sum_q : i_pending_sum_q), + .req_mxr ((ptw_owner_next == PTW_SRC_D) ? d_pending_mxr_q : i_pending_mxr_q), + .satp_value (satp_value), + .mem_req_valid (ptw_mem_req_valid), + .mem_req_ready (ptw_mem_req_ready), + .mem_req_addr (ptw_mem_req_addr), + .mem_resp_valid(ptw_mem_resp_valid), + .mem_resp_data (ptw_mem_resp_data), + .resp_valid (ptw_resp_valid), + .resp_fault (ptw_resp_fault), + .resp_paddr (ptw_resp_paddr), + .refill_valid (ptw_refill_valid), + .refill_vpn (ptw_refill_vpn), + .refill_ppn (ptw_refill_ppn), + .refill_level (ptw_refill_level), + .refill_mode (ptw_refill_mode), + .refill_asid (ptw_refill_asid), + .refill_g (ptw_refill_g), + .refill_u (ptw_refill_u), + .refill_r (ptw_refill_r), + .refill_w (ptw_refill_w), + .refill_x (ptw_refill_x), + .refill_a (ptw_refill_a), + .refill_d (ptw_refill_d) + ); + +endmodule -- cgit v1.2.3 From e0948e3fc10029ba4bb4d48d7b5daae94fe575b9 Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Sat, 7 Nov 2026 03:16:17 +0800 Subject: refactor: align RTL module names with files --- rv64cpu/rtl/core/execute/instruction_decoder.sv | 2 +- rv64cpu/rtl/core/execute/integer_alu.sv | 2 +- rv64cpu/rtl/core/fpu/fpu.sv | 2 +- rv64cpu/rtl/core/mmu/mmu.sv | 2 +- rv64cpu/rtl/core/pipeline/ex_stage.sv | 2 +- rv64cpu/rtl/core/pipeline/id_stage.sv | 6 +++--- rv64cpu/rtl/core/privileged/trap_controller.sv | 2 +- rv64cpu/rtl/core/registers/fpr_file.sv | 2 +- rv64cpu/rtl/core/registers/gpr_file.sv | 2 +- rv64cpu/rtl/core/rv64_core.sv | 8 ++++---- 10 files changed, 15 insertions(+), 15 deletions(-) (limited to 'rv64cpu/rtl/core/mmu/mmu.sv') diff --git a/rv64cpu/rtl/core/execute/instruction_decoder.sv b/rv64cpu/rtl/core/execute/instruction_decoder.sv index c39a637..14d9559 100644 --- a/rv64cpu/rtl/core/execute/instruction_decoder.sv +++ b/rv64cpu/rtl/core/execute/instruction_decoder.sv @@ -19,7 +19,7 @@ // Translates 32-bit instructions into control signals for the pipeline. // C is handled by the IF-stage decompressor before this decoder. -module decoder +module instruction_decoder import rv64_pkg::*; ( input logic [31:0] instr, // 32-bit instruction diff --git a/rv64cpu/rtl/core/execute/integer_alu.sv b/rv64cpu/rtl/core/execute/integer_alu.sv index 08635ce..833f902 100644 --- a/rv64cpu/rtl/core/execute/integer_alu.sv +++ b/rv64cpu/rtl/core/execute/integer_alu.sv @@ -17,7 +17,7 @@ // File path: rtl/core/alu.sv // Description: 64-bit Arithmetic Logic Unit (ALU) -module alu +module integer_alu import rv64_pkg::*; ( input alu_op_t alu_op, // ALU operation select (from decoder) diff --git a/rv64cpu/rtl/core/fpu/fpu.sv b/rv64cpu/rtl/core/fpu/fpu.sv index a1962e1..9e9494d 100644 --- a/rv64cpu/rtl/core/fpu/fpu.sv +++ b/rv64cpu/rtl/core/fpu/fpu.sv @@ -4,7 +4,7 @@ // File path: rtl/core/fpu/fpu_unit.sv // Description: RV64F/RV64D floating-point execution unit. -module fpu_unit +module fpu import rv64_pkg::*; ( input fp_op_t fp_op, diff --git a/rv64cpu/rtl/core/mmu/mmu.sv b/rv64cpu/rtl/core/mmu/mmu.sv index 169bf81..60c4afa 100644 --- a/rv64cpu/rtl/core/mmu/mmu.sv +++ b/rv64cpu/rtl/core/mmu/mmu.sv @@ -17,7 +17,7 @@ // File path: rtl/core/mmu/mmu_top.sv // Description: MMU top-level integrating iTLB + dTLB + shared PTW -module mmu_top +module mmu import rv64_pkg::*; #( parameter int ITLB_ENTRIES = 16, diff --git a/rv64cpu/rtl/core/pipeline/ex_stage.sv b/rv64cpu/rtl/core/pipeline/ex_stage.sv index 287bfd7..2758ffc 100644 --- a/rv64cpu/rtl/core/pipeline/ex_stage.sv +++ b/rv64cpu/rtl/core/pipeline/ex_stage.sv @@ -88,7 +88,7 @@ module ex_stage // -------------- // Instantiate the core computing engine ALU - alu alu_inst ( + integer_alu alu_inst ( .alu_op (ex_alu_op), .operand_a (alu_operand_a), .operand_b (alu_operand_b), diff --git a/rv64cpu/rtl/core/pipeline/id_stage.sv b/rv64cpu/rtl/core/pipeline/id_stage.sv index 9003b42..1cf447a 100644 --- a/rv64cpu/rtl/core/pipeline/id_stage.sv +++ b/rv64cpu/rtl/core/pipeline/id_stage.sv @@ -108,7 +108,7 @@ module id_stage // Instruction Decoder Instantiation - decoder u_decoder ( + instruction_decoder u_decoder ( .instr (if_instr), .priv_mode (csr_priv_mode), .mstatus_tsr (csr_mstatus_tsr), @@ -164,7 +164,7 @@ module id_stage ); // Register File Instantiation - regfile u_regfile ( + gpr_file u_regfile ( .clk (clk), .rst (rst), @@ -180,7 +180,7 @@ module id_stage .rd_wdata (wb_rd_wdata) ); - fp_regfile u_fp_regfile ( + fpr_file u_fp_regfile ( .clk (clk), .rst (rst), .fs1_addr (rs1_addr), diff --git a/rv64cpu/rtl/core/privileged/trap_controller.sv b/rv64cpu/rtl/core/privileged/trap_controller.sv index 0969fdc..246b392 100644 --- a/rv64cpu/rtl/core/privileged/trap_controller.sv +++ b/rv64cpu/rtl/core/privileged/trap_controller.sv @@ -18,7 +18,7 @@ // Description: Privileged-level Trap Controller (Exception and Interrupt Handling) // Detects exceptions/interrupts, triggers context saving, and generates global pipeline flush and PC jump signals -module trap_ctrl +module trap_controller import rv64_pkg::*; import csr_pkg::*; ( diff --git a/rv64cpu/rtl/core/registers/fpr_file.sv b/rv64cpu/rtl/core/registers/fpr_file.sv index 67e83f9..7522b5f 100644 --- a/rv64cpu/rtl/core/registers/fpr_file.sv +++ b/rv64cpu/rtl/core/registers/fpr_file.sv @@ -4,7 +4,7 @@ // File path: rtl/core/fp_regfile.sv // Description: 32-entry 64-bit floating-point register file for RV64F/RV64D. -module fp_regfile +module fpr_file import rv64_pkg::*; ( input logic clk, diff --git a/rv64cpu/rtl/core/registers/gpr_file.sv b/rv64cpu/rtl/core/registers/gpr_file.sv index dbc3c04..4ddf200 100644 --- a/rv64cpu/rtl/core/registers/gpr_file.sv +++ b/rv64cpu/rtl/core/registers/gpr_file.sv @@ -17,7 +17,7 @@ // File path: rtl/core/regfile.sv // Description: 64-bit Register File -module regfile +module gpr_file import rv64_pkg::*; ( input logic clk, // Clock signal diff --git a/rv64cpu/rtl/core/rv64_core.sv b/rv64cpu/rtl/core/rv64_core.sv index 51c64f8..630fc3d 100644 --- a/rv64cpu/rtl/core/rv64_core.sv +++ b/rv64cpu/rtl/core/rv64_core.sv @@ -18,7 +18,7 @@ // Description: Richard CPU core top-level wrapper (Core Top) // Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit -module richard_core +module rv64_core import rv64_pkg::*; import csr_pkg::*; ( @@ -389,7 +389,7 @@ module richard_core end end - mmu_top u_mmu_top ( + mmu u_mmu_top ( .clk (clk), .rst (rst), .satp_value (csr_satp_value), @@ -763,7 +763,7 @@ module richard_core .ex_branch_target (ex_branch_target_out) ); - fpu_unit u_fpu_unit ( + fpu u_fpu_unit ( .fp_op (ex_fp_op_in), .fp_fmt (ex_fp_fmt_in), .rm ((ex_fp_rm_in == 3'b111) ? csr_frm_value : ex_fp_rm_in), @@ -1171,7 +1171,7 @@ module richard_core .csr_illegal_access (csr_illegal_access) ); - trap_ctrl u_trap_ctrl ( + trap_controller u_trap_ctrl ( .wb_pc (wb_pc_in), .trap_illegal_instr (trap_illegal_instr), .trap_is_ecall (trap_is_ecall), -- cgit v1.2.3