From 6f57dd79572c177b775a934bee54ceb85a55c28a Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Sat, 7 Nov 2026 03:14:46 +0800 Subject: refactor: rename RTL source files --- rv64cpu/rtl/core/registers/fp_regfile.sv | 41 ------------------- rv64cpu/rtl/core/registers/fpr_file.sv | 41 +++++++++++++++++++ rv64cpu/rtl/core/registers/gpr_file.sv | 67 ++++++++++++++++++++++++++++++++ rv64cpu/rtl/core/registers/regfile.sv | 67 -------------------------------- 4 files changed, 108 insertions(+), 108 deletions(-) delete mode 100644 rv64cpu/rtl/core/registers/fp_regfile.sv create mode 100644 rv64cpu/rtl/core/registers/fpr_file.sv create mode 100644 rv64cpu/rtl/core/registers/gpr_file.sv delete mode 100644 rv64cpu/rtl/core/registers/regfile.sv (limited to 'rv64cpu/rtl/core/registers') diff --git a/rv64cpu/rtl/core/registers/fp_regfile.sv b/rv64cpu/rtl/core/registers/fp_regfile.sv deleted file mode 100644 index 67e83f9..0000000 --- a/rv64cpu/rtl/core/registers/fp_regfile.sv +++ /dev/null @@ -1,41 +0,0 @@ -// Richard CPU -// Copyright (C) 2026 Richard Qin - -// File path: rtl/core/fp_regfile.sv -// Description: 32-entry 64-bit floating-point register file for RV64F/RV64D. - -module fp_regfile - import rv64_pkg::*; -( - input logic clk, - input logic rst, - - input logic [4:0] fs1_addr, - input logic [4:0] fs2_addr, - input logic [4:0] fs3_addr, - output logic [XLEN-1:0] fs1_rdata, - output logic [XLEN-1:0] fs2_rdata, - output logic [XLEN-1:0] fs3_rdata, - - input logic fp_write_en, - input logic [4:0] fd_addr, - input logic [XLEN-1:0] fd_wdata -); - - logic [XLEN-1:0] regs [0:31]; - - assign fs1_rdata = (fp_write_en && (fs1_addr == fd_addr)) ? fd_wdata : regs[fs1_addr]; - assign fs2_rdata = (fp_write_en && (fs2_addr == fd_addr)) ? fd_wdata : regs[fs2_addr]; - assign fs3_rdata = (fp_write_en && (fs3_addr == fd_addr)) ? fd_wdata : regs[fs3_addr]; - - always_ff @(posedge clk) begin - if (rst) begin - for (int unsigned reg_idx = 0; reg_idx < 32; reg_idx++) begin - regs[reg_idx] <= '0; - end - end else if (fp_write_en) begin - regs[fd_addr] <= fd_wdata; - end - end - -endmodule diff --git a/rv64cpu/rtl/core/registers/fpr_file.sv b/rv64cpu/rtl/core/registers/fpr_file.sv new file mode 100644 index 0000000..67e83f9 --- /dev/null +++ b/rv64cpu/rtl/core/registers/fpr_file.sv @@ -0,0 +1,41 @@ +// Richard CPU +// Copyright (C) 2026 Richard Qin + +// File path: rtl/core/fp_regfile.sv +// Description: 32-entry 64-bit floating-point register file for RV64F/RV64D. + +module fp_regfile + import rv64_pkg::*; +( + input logic clk, + input logic rst, + + input logic [4:0] fs1_addr, + input logic [4:0] fs2_addr, + input logic [4:0] fs3_addr, + output logic [XLEN-1:0] fs1_rdata, + output logic [XLEN-1:0] fs2_rdata, + output logic [XLEN-1:0] fs3_rdata, + + input logic fp_write_en, + input logic [4:0] fd_addr, + input logic [XLEN-1:0] fd_wdata +); + + logic [XLEN-1:0] regs [0:31]; + + assign fs1_rdata = (fp_write_en && (fs1_addr == fd_addr)) ? fd_wdata : regs[fs1_addr]; + assign fs2_rdata = (fp_write_en && (fs2_addr == fd_addr)) ? fd_wdata : regs[fs2_addr]; + assign fs3_rdata = (fp_write_en && (fs3_addr == fd_addr)) ? fd_wdata : regs[fs3_addr]; + + always_ff @(posedge clk) begin + if (rst) begin + for (int unsigned reg_idx = 0; reg_idx < 32; reg_idx++) begin + regs[reg_idx] <= '0; + end + end else if (fp_write_en) begin + regs[fd_addr] <= fd_wdata; + end + end + +endmodule diff --git a/rv64cpu/rtl/core/registers/gpr_file.sv b/rv64cpu/rtl/core/registers/gpr_file.sv new file mode 100644 index 0000000..dbc3c04 --- /dev/null +++ b/rv64cpu/rtl/core/registers/gpr_file.sv @@ -0,0 +1,67 @@ +// Richard CPU +// Copyright (C) 2026 Richard Qin + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// File path: rtl/core/regfile.sv +// Description: 64-bit Register File + +module regfile + import rv64_pkg::*; +( + input logic clk, // Clock signal + input logic rst, // Reset signal active high + + // Read port 1 + input logic [4:0] rs1_addr, // Read address 1 + output logic [XLEN-1:0] rs1_rdata, // Read data 1 + + // Read port 2 + input logic [4:0] rs2_addr, // Read address 2 + output logic [XLEN-1:0] rs2_rdata, // Read data 2 + + // Write port + input logic [4:0] rd_addr, // Write address + input logic [XLEN-1:0] rd_wdata, // Write data + input logic reg_write_en // Write enable signal +); + + // Register file storage + logic [XLEN-1:0] regs [0:31]; + + // Read Logic (combinational logic) + // Internal bypass: If reading the same register as currently being written, + // forward the write data immediately. + assign rs1_rdata = (rs1_addr == 5'b0) ? '0 : + ((rs1_addr == rd_addr) && reg_write_en) ? rd_wdata : + regs[rs1_addr]; + + assign rs2_rdata = (rs2_addr == 5'b0) ? '0 : + ((rs2_addr == rd_addr) && reg_write_en) ? rd_wdata : + regs[rs2_addr]; + + // Write Logic (sequential logic) + always_ff @(posedge clk) begin + if (rst) begin + for (int i = 0; i < 32; i++) begin + regs[i] <= '0; + end + end else begin + if (reg_write_en && rd_addr != 5'b0) begin + regs[rd_addr] <= rd_wdata; + end + end + end + +endmodule diff --git a/rv64cpu/rtl/core/registers/regfile.sv b/rv64cpu/rtl/core/registers/regfile.sv deleted file mode 100644 index dbc3c04..0000000 --- a/rv64cpu/rtl/core/registers/regfile.sv +++ /dev/null @@ -1,67 +0,0 @@ -// Richard CPU -// Copyright (C) 2026 Richard Qin - -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. - -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. - -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// File path: rtl/core/regfile.sv -// Description: 64-bit Register File - -module regfile - import rv64_pkg::*; -( - input logic clk, // Clock signal - input logic rst, // Reset signal active high - - // Read port 1 - input logic [4:0] rs1_addr, // Read address 1 - output logic [XLEN-1:0] rs1_rdata, // Read data 1 - - // Read port 2 - input logic [4:0] rs2_addr, // Read address 2 - output logic [XLEN-1:0] rs2_rdata, // Read data 2 - - // Write port - input logic [4:0] rd_addr, // Write address - input logic [XLEN-1:0] rd_wdata, // Write data - input logic reg_write_en // Write enable signal -); - - // Register file storage - logic [XLEN-1:0] regs [0:31]; - - // Read Logic (combinational logic) - // Internal bypass: If reading the same register as currently being written, - // forward the write data immediately. - assign rs1_rdata = (rs1_addr == 5'b0) ? '0 : - ((rs1_addr == rd_addr) && reg_write_en) ? rd_wdata : - regs[rs1_addr]; - - assign rs2_rdata = (rs2_addr == 5'b0) ? '0 : - ((rs2_addr == rd_addr) && reg_write_en) ? rd_wdata : - regs[rs2_addr]; - - // Write Logic (sequential logic) - always_ff @(posedge clk) begin - if (rst) begin - for (int i = 0; i < 32; i++) begin - regs[i] <= '0; - end - end else begin - if (reg_write_en && rd_addr != 5'b0) begin - regs[rd_addr] <= rd_wdata; - end - end - end - -endmodule -- cgit v1.2.3