From 1d4ed362e1caccc22aa4bd0dc2a9316e999f849a Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Wed, 18 Mar 2026 19:48:35 +0800 Subject: Add fibonacci tests and fix bugs --- rv64cpu/rtl/core/regfile.sv | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'rv64cpu/rtl') diff --git a/rv64cpu/rtl/core/regfile.sv b/rv64cpu/rtl/core/regfile.sv index 640890d..dbc3c04 100644 --- a/rv64cpu/rtl/core/regfile.sv +++ b/rv64cpu/rtl/core/regfile.sv @@ -41,8 +41,15 @@ module regfile logic [XLEN-1:0] regs [0:31]; // Read Logic (combinational logic) - assign rs1_rdata = (rs1_addr == 5'b0) ? '0 : regs[rs1_addr]; - assign rs2_rdata = (rs2_addr == 5'b0) ? '0 : regs[rs2_addr]; + // Internal bypass: If reading the same register as currently being written, + // forward the write data immediately. + assign rs1_rdata = (rs1_addr == 5'b0) ? '0 : + ((rs1_addr == rd_addr) && reg_write_en) ? rd_wdata : + regs[rs1_addr]; + + assign rs2_rdata = (rs2_addr == 5'b0) ? '0 : + ((rs2_addr == rd_addr) && reg_write_en) ? rd_wdata : + regs[rs2_addr]; // Write Logic (sequential logic) always_ff @(posedge clk) begin -- cgit v1.2.3