From 639212a826659c591db3202607c4a47e1049b92a Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Tue, 7 Apr 2026 22:42:49 +0800 Subject: refactor: standardize interrupt signal naming across the codebase --- rv64cpu/rtl/core/csr_unit.sv | 52 ++++++++++++++++++------------------- rv64cpu/rtl/core/include/csr_pkg.sv | 18 ++++++------- rv64cpu/rtl/core/richard_core.sv | 38 +++++++++++++-------------- rv64cpu/rtl/core/trap_ctrl.sv | 24 ++++++++--------- 4 files changed, 66 insertions(+), 66 deletions(-) (limited to 'rv64cpu/rtl') diff --git a/rv64cpu/rtl/core/csr_unit.sv b/rv64cpu/rtl/core/csr_unit.sv index 0427eeb..3aefe10 100644 --- a/rv64cpu/rtl/core/csr_unit.sv +++ b/rv64cpu/rtl/core/csr_unit.sv @@ -201,10 +201,10 @@ module csr_unit if (csr_write_en && csr_is_writable(csr_addr_canonical)) begin unique case (csr_addr_canonical) CSR_MSTATUS: begin - logic [XLEN-1:0] next_val; - next_val = csr_write_next(mstatus_reg, csr_rs1_data, csr_op); - mstatus_reg <= next_val; - sstatus_reg <= mirror_mstatus_to_sstatus(sstatus_reg, next_val); + logic [XLEN-1:0] next_data; + next_data = csr_write_next(mstatus_reg, csr_rs1_data, csr_op); + mstatus_reg <= next_data; + sstatus_reg <= mirror_mstatus_to_sstatus(sstatus_reg, next_data); end CSR_MEDELEG: medeleg_reg <= csr_write_next(medeleg_reg, csr_rs1_data, csr_op); CSR_MIDELEG: mideleg_reg <= csr_write_next(mideleg_reg, csr_rs1_data, csr_op); @@ -321,18 +321,18 @@ module csr_unit // Apply the CSR op semantics (write/set/clear) for a single register. function automatic logic [XLEN-1:0] csr_write_next( - input logic [XLEN-1:0] current_val, - input logic [XLEN-1:0] write_val, + input logic [XLEN-1:0] current_data, + input logic [XLEN-1:0] write_data, input logic [2:0] op_code ); - logic [XLEN-1:0] next_val; + logic [XLEN-1:0] next_data; unique case (op_code) - 3'b001, 3'b101: next_val = write_val; // CSRRW / CSRRWI - 3'b010, 3'b110: next_val = current_val | write_val; // CSRRS / CSRRSI - 3'b011, 3'b111: next_val = current_val & ~write_val; // CSRRC / CSRRCI - default: next_val = current_val; + 3'b001, 3'b101: next_data = write_data; // CSRRW / CSRRWI + 3'b010, 3'b110: next_data = current_data | write_data; // CSRRS / CSRRSI + 3'b011, 3'b111: next_data = current_data & ~write_data; // CSRRC / CSRRCI + default: next_data = current_data; endcase - return next_val; + return next_data; endfunction function automatic bit csr_is_writable(input logic [11:0] addr); @@ -393,26 +393,26 @@ module csr_unit function automatic logic [XLEN-1:0] apply_sstatus_to_mstatus( input logic [XLEN-1:0] mstatus_cur, - input logic [XLEN-1:0] sstatus_val + input logic [XLEN-1:0] sstatus_data ); - logic [XLEN-1:0] next_val; - next_val = mstatus_cur; - next_val[SSTATUS_SIE_BIT] = sstatus_val[SSTATUS_SIE_BIT]; - next_val[SSTATUS_SPIE_BIT] = sstatus_val[SSTATUS_SPIE_BIT]; - next_val[SSTATUS_SPP_BIT] = sstatus_val[SSTATUS_SPP_BIT]; - return next_val; + logic [XLEN-1:0] next_data; + next_data = mstatus_cur; + next_data[SSTATUS_SIE_BIT] = sstatus_data[SSTATUS_SIE_BIT]; + next_data[SSTATUS_SPIE_BIT] = sstatus_data[SSTATUS_SPIE_BIT]; + next_data[SSTATUS_SPP_BIT] = sstatus_data[SSTATUS_SPP_BIT]; + return next_data; endfunction function automatic logic [XLEN-1:0] mirror_mstatus_to_sstatus( input logic [XLEN-1:0] sstatus_cur, - input logic [XLEN-1:0] mstatus_val + input logic [XLEN-1:0] mstatus_data ); - logic [XLEN-1:0] next_val; - next_val = sstatus_cur; - next_val[SSTATUS_SIE_BIT] = mstatus_val[SSTATUS_SIE_BIT]; - next_val[SSTATUS_SPIE_BIT] = mstatus_val[SSTATUS_SPIE_BIT]; - next_val[SSTATUS_SPP_BIT] = mstatus_val[SSTATUS_SPP_BIT]; - return next_val; + logic [XLEN-1:0] next_data; + next_data = sstatus_cur; + next_data[SSTATUS_SIE_BIT] = mstatus_data[SSTATUS_SIE_BIT]; + next_data[SSTATUS_SPIE_BIT] = mstatus_data[SSTATUS_SPIE_BIT]; + next_data[SSTATUS_SPP_BIT] = mstatus_data[SSTATUS_SPP_BIT]; + return next_data; endfunction // Pack the discrete FP status bits into the architectural FCSR layout. diff --git a/rv64cpu/rtl/core/include/csr_pkg.sv b/rv64cpu/rtl/core/include/csr_pkg.sv index a225da2..a908538 100644 --- a/rv64cpu/rtl/core/include/csr_pkg.sv +++ b/rv64cpu/rtl/core/include/csr_pkg.sv @@ -102,16 +102,16 @@ package csr_pkg; // Interrupt Cause Codes (mcause.Interrupt == 1) // --------------------------------- // User Mode Interrupts - localparam logic [XLEN-1:0] INT_U_SOFTWARE = 64'd0; // User Mode Software Interrupt - localparam logic [XLEN-1:0] INT_U_TIMER = 64'd4; // User Mode Timer Interrupt - localparam logic [XLEN-1:0] INT_U_EXTERNAL = 64'd8; // User Mode External Interrupt + localparam logic [XLEN-1:0] INTERRUPT_U_SOFTWARE = 64'd0; // User Mode Software Interrupt + localparam logic [XLEN-1:0] INTERRUPT_U_TIMER = 64'd4; // User Mode Timer Interrupt + localparam logic [XLEN-1:0] INTERRUPT_U_EXTERNAL = 64'd8; // User Mode External Interrupt // Supervisor Mode Interrupts - localparam logic [XLEN-1:0] INT_S_SOFTWARE = 64'd1; // Supervisor Mode Software Interrupt - localparam logic [XLEN-1:0] INT_S_TIMER = 64'd5; // Supervisor Mode Timer Interrupt - localparam logic [XLEN-1:0] INT_S_EXTERNAL = 64'd9; // Supervisor Mode External Interrupt + localparam logic [XLEN-1:0] INTERRUPT_S_SOFTWARE = 64'd1; // Supervisor Mode Software Interrupt + localparam logic [XLEN-1:0] INTERRUPT_S_TIMER = 64'd5; // Supervisor Mode Timer Interrupt + localparam logic [XLEN-1:0] INTERRUPT_S_EXTERNAL = 64'd9; // Supervisor Mode External Interrupt // Machine Mode Interrupts - localparam logic [XLEN-1:0] INT_M_SOFTWARE = 64'd3; // Machine Mode Software Interrupt - localparam logic [XLEN-1:0] INT_M_TIMER = 64'd7; // Machine Mode Timer Interrupt - localparam logic [XLEN-1:0] INT_M_EXTERNAL = 64'd11; // Machine Mode External Interrupt + localparam logic [XLEN-1:0] INTERRUPT_M_SOFTWARE = 64'd3; // Machine Mode Software Interrupt + localparam logic [XLEN-1:0] INTERRUPT_M_TIMER = 64'd7; // Machine Mode Timer Interrupt + localparam logic [XLEN-1:0] INTERRUPT_M_EXTERNAL = 64'd11; // Machine Mode External Interrupt endpackage diff --git a/rv64cpu/rtl/core/richard_core.sv b/rv64cpu/rtl/core/richard_core.sv index ad75cc8..a841253 100644 --- a/rv64cpu/rtl/core/richard_core.sv +++ b/rv64cpu/rtl/core/richard_core.sv @@ -37,9 +37,9 @@ module richard_core input logic [63:0] dmem_rdata, // Interface 3: External Interrupt Sources - input logic ext_timer_int, - input logic ext_software_int, - input logic ext_external_int + input logic ext_timer_interrupt, + input logic ext_software_interrupt, + input logic ext_external_interrupt ); localparam int CSR_MSTATUS_MIE_BIT = 3; @@ -159,7 +159,7 @@ module richard_core logic [4:0] wb_rs1_addr_in; logic [XLEN-1:0] wb_imm_in; logic wb_illegal_instr_in, wb_is_ecall_in, wb_is_ebreak_in, wb_is_mret_in, wb_is_sret_in; - logic wb_load_fault_flag, wb_store_fault_flag; + logic wb_load_fault, wb_store_fault; logic [XLEN-1:0] wb_fault_addr_in; // (10) WB Stage Outputs (to RegFile & CSR Unit) @@ -182,8 +182,8 @@ module richard_core logic [XLEN-1:0] csr_sepc_value; logic [XLEN-1:0] csr_satp_value; logic [XLEN-1:0] csr_trap_vector_value; - logic csr_trap_to_s_mode_flag; - logic csr_illegal_access_flag; + logic csr_trap_to_s_mode; + logic csr_illegal_access; // (11) Exception / Trap bus logic trap_illegal_instr, trap_is_ecall, trap_is_ebreak, trap_is_mret, trap_is_sret; @@ -203,7 +203,7 @@ module richard_core logic [XLEN-1:0] trap_ctrl_mepc; logic [XLEN-1:0] trap_ctrl_mcause; logic [XLEN-1:0] trap_ctrl_mtval; - logic trap_ctrl_to_s_mode_flag; + logic trap_ctrl_to_s_mode; logic trap_ctrl_mret_en; logic trap_ctrl_sret_en; logic csr_mstatus_mie; @@ -591,8 +591,8 @@ module richard_core .wb_is_ebreak (wb_is_ebreak_in), .wb_is_mret (wb_is_mret_in), .wb_is_sret (wb_is_sret_in), - .wb_load_fault (wb_load_fault_flag), - .wb_store_fault (wb_store_fault_flag), + .wb_load_fault (wb_load_fault), + .wb_store_fault (wb_store_fault), .wb_fault_addr (wb_fault_addr_in) ); @@ -618,11 +618,11 @@ module richard_core .mem_wb_is_ebreak (wb_is_ebreak_in), .mem_wb_is_mret (wb_is_mret_in), .mem_wb_is_sret (wb_is_sret_in), - .mem_wb_load_fault (wb_load_fault_flag), - .mem_wb_store_fault (wb_store_fault_flag), + .mem_wb_load_fault (wb_load_fault), + .mem_wb_store_fault (wb_store_fault), .mem_wb_fault_addr (wb_fault_addr_in), .csr_rdata (csr_rdata), - .csr_illegal_access (csr_illegal_access_flag), + .csr_illegal_access (csr_illegal_access), .wb_rd_wdata (wb_rd_wdata), .wb_rd_addr (wb_rd_addr), .wb_reg_write_en (wb_reg_write_en_out), @@ -650,7 +650,7 @@ module richard_core .csr_addr (csr_addr), .csr_rs1_data (csr_rs1_data), .trap_ctrl_trigger (trap_ctrl_trigger), - .trap_ctrl_to_s_mode(trap_ctrl_to_s_mode_flag), + .trap_ctrl_to_s_mode(trap_ctrl_to_s_mode), .trap_ctrl_mepc (trap_ctrl_mepc), .trap_ctrl_mcause (trap_ctrl_mcause), .trap_ctrl_mtval (trap_ctrl_mtval), @@ -670,8 +670,8 @@ module richard_core .csr_trap_vector (), .csr_trap_to_s_mode (), .csr_trap_vector_next (csr_trap_vector_value), - .csr_trap_to_s_mode_next(csr_trap_to_s_mode_flag), - .csr_illegal_access (csr_illegal_access_flag) + .csr_trap_to_s_mode_next(csr_trap_to_s_mode), + .csr_illegal_access (csr_illegal_access) ); trap_ctrl u_trap_ctrl ( @@ -688,9 +688,9 @@ module richard_core .trap_store_page_fault(trap_store_page_fault), .trap_bad_addr (trap_bad_addr), .trap_bad_instr (trap_bad_instr), - .ext_timer_int (ext_timer_int), - .ext_software_int (ext_software_int), - .ext_external_int (ext_external_int), + .ext_timer_interrupt (ext_timer_interrupt), + .ext_software_interrupt (ext_software_interrupt), + .ext_external_interrupt (ext_external_interrupt), .csr_mstatus_mie (csr_mstatus_mie), .csr_mtvec (csr_mtvec_base), .csr_stvec (csr_stvec_base), @@ -703,7 +703,7 @@ module richard_core .trap_mepc (trap_ctrl_mepc), .trap_mcause (trap_ctrl_mcause), .trap_mtval (trap_ctrl_mtval), - .trap_to_s_mode (trap_ctrl_to_s_mode_flag), + .trap_to_s_mode (trap_ctrl_to_s_mode), .mret_en (trap_ctrl_mret_en), .sret_en (trap_ctrl_sret_en), .trap_flush_req (trap_flush_req), diff --git a/rv64cpu/rtl/core/trap_ctrl.sv b/rv64cpu/rtl/core/trap_ctrl.sv index c5593ea..55278d9 100644 --- a/rv64cpu/rtl/core/trap_ctrl.sv +++ b/rv64cpu/rtl/core/trap_ctrl.sv @@ -38,9 +38,9 @@ module trap_ctrl input logic [INST_WIDTH-1:0] trap_bad_instr, // Interrupt pin from external source (asynchronous signal) - input logic ext_timer_int, // M-Mode Machine Timer Interrupt (MTIP) - input logic ext_software_int, // M-Mode Software Interrupt (MSIP) - input logic ext_external_int, // M-Mode External Interrupt (MEIP) + input logic ext_timer_interrupt, // M-Mode Machine Timer Interrupt (MTIP) + input logic ext_software_interrupt, // M-Mode Software Interrupt (MSIP) + input logic ext_external_interrupt, // M-Mode External Interrupt (MEIP) // Status read from CSR Unit input logic csr_mstatus_mie, // Global interrupt enable (MIE) @@ -128,22 +128,22 @@ module trap_ctrl // Interrupt Detection - Asynchronous, Protected by MIE logic has_interrupt; - logic [XLEN-1:0] int_cause; + logic [XLEN-1:0] interrupt_cause; always_comb begin has_interrupt = 1'b0; - int_cause = '0; + interrupt_cause = '0; if (csr_mstatus_mie) begin - if (ext_external_int) begin + if (ext_external_interrupt) begin has_interrupt = 1'b1; - int_cause = INTERRUPT_BIT | INT_M_EXTERNAL; - end else if (ext_software_int) begin + interrupt_cause = INTERRUPT_BIT | INTERRUPT_M_EXTERNAL; + end else if (ext_software_interrupt) begin has_interrupt = 1'b1; - int_cause = INTERRUPT_BIT | INT_M_SOFTWARE; - end else if (ext_timer_int) begin + interrupt_cause = INTERRUPT_BIT | INTERRUPT_M_SOFTWARE; + end else if (ext_timer_interrupt) begin has_interrupt = 1'b1; - int_cause = INTERRUPT_BIT | INT_M_TIMER; + interrupt_cause = INTERRUPT_BIT | INTERRUPT_M_TIMER; end end end @@ -153,7 +153,7 @@ module trap_ctrl logic trap_is_interrupt; assign trap_is_interrupt = has_interrupt; - assign trap_cause_value = has_interrupt ? int_cause : sync_cause; + assign trap_cause_value = has_interrupt ? interrupt_cause : sync_cause; assign trap_mtval_value = has_interrupt ? '0 : sync_mtval; assign trap_trigger = has_interrupt | has_sync_exception; -- cgit v1.2.3