From bd1d53990e8e7b94a2126682a3146de01a0c76ad Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Wed, 18 Mar 2026 00:03:09 +0800 Subject: Memory Stage and MEM/WB pipeline stage register --- rv64cpu/rtl/core/mem_stage.sv | 214 +++++++++++++++++++++++++++++++++++++++++ rv64cpu/rtl/core/mem_wb_reg.sv | 132 +++++++++++++++++++++++++ 2 files changed, 346 insertions(+) create mode 100644 rv64cpu/rtl/core/mem_stage.sv create mode 100644 rv64cpu/rtl/core/mem_wb_reg.sv (limited to 'rv64cpu/rtl') diff --git a/rv64cpu/rtl/core/mem_stage.sv b/rv64cpu/rtl/core/mem_stage.sv new file mode 100644 index 0000000..467ba1b --- /dev/null +++ b/rv64cpu/rtl/core/mem_stage.sv @@ -0,0 +1,214 @@ +// Richard CPU +// Copyright (C) 2026 Richard Qin + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// File path: rtl/core/mem_stage.sv +// Description: Memory Stage +// Latches results from the EX stage and bypassed control signals from ID/EX. +// Supports stall and flush operations. + +module mem_stage + import rv64_pkg::*; +( + // Inputs from EX/MEM pipeline register + input logic [XLEN-1:0] mem_alu_result, // Used as memory address or ALU result + input logic mem_branch_taken, + input logic [XLEN-1:0] mem_branch_target, + input logic [XLEN-1:0] mem_rs1_rdata, + input logic [XLEN-1:0] mem_rs2_rdata, // Store data + input logic [4:0] mem_rs1_addr, + input logic [XLEN-1:0] mem_pc, + input logic [XLEN-1:0] mem_imm, + + // Memory Control + input logic mem_is_load, + input logic mem_is_store, + input logic [2:0] mem_mem_size, // LB/LH/LW/LD/LBU/LHU/LWU + + // Writeback Control + input logic mem_reg_write_en, + input logic [4:0] mem_rd_addr, + input logic [1:0] mem_wb_sel, + + // Exceptions and System (bypassed through or generated) + input logic mem_is_csr, + input logic [2:0] mem_csr_op, + input logic mem_illegal_instr, + input logic mem_is_ecall, + input logic mem_is_ebreak, + input logic mem_is_mret, + input logic mem_is_sret, + input logic mem_is_wfi, + input logic mem_is_sfence_vma, + input logic mem_is_fence, + input logic mem_is_fence_i, + + // Data Memory Interface (to Data Cache / Memory Controller) + output logic dmem_read_req, + output logic dmem_write_req, + output logic [XLEN-1:0] dmem_addr, + output logic [XLEN-1:0] dmem_wdata, + output logic [7:0] dmem_wstrb, // Write strobe depending on size + input logic dmem_req_ready, // Wait signal from D-Cache + input logic dmem_rsp_valid, // Data valid from D-Cache + input logic [XLEN-1:0] dmem_rdata, + + // Outputs to MEM/WB Pipeline Register + output logic [XLEN-1:0] mem_wb_alu_result, + output logic [XLEN-1:0] mem_wb_mem_rdata, + output logic [XLEN-1:0] mem_wb_pc, + + output logic mem_wb_reg_write_en, + output logic [4:0] mem_wb_rd_addr, + output logic [1:0] mem_wb_wb_sel, + + output logic mem_wb_is_csr, + output logic [2:0] mem_wb_csr_op, + output logic [XLEN-1:0] mem_wb_rs1_rdata, + output logic [4:0] mem_wb_rs1_addr, + output logic [XLEN-1:0] mem_wb_imm, + + output logic mem_wb_illegal_instr, + output logic mem_wb_is_ecall, + output logic mem_wb_is_ebreak, + output logic mem_wb_is_mret, + output logic mem_wb_is_sret, + + // Control to Hazard Unit / Stall Logic + output logic mem_stall_req // Stall pipeline if D-Cache doesn't respond +); + + logic [XLEN-1:0] load_data_aligned; + logic [XLEN-1:0] store_data_aligned; + logic [7:0] write_strobe; + + // -------------------------- + // Memory Request Logic + assign dmem_read_req = mem_is_load; + assign dmem_write_req = mem_is_store; + assign dmem_addr = mem_alu_result; // ALU result is the computed address + + // -------------------------- + // Stall generation: Stall if memory request is not yet ready or valid + // For a simple synchronous SRAM, this might be 0, but for cache it will depend on hits/misses + // -------------------------- + always_comb begin + if ((mem_is_load || mem_is_store) && (!dmem_req_ready || (mem_is_load && !dmem_rsp_valid))) begin + mem_stall_req = 1'b1; + end else begin + mem_stall_req = 1'b0; + end + end + + // -------------------------- + // Store Data Alignment and Strobe Generation + // -------------------------- + always_comb begin + logic [2:0] align_offset; + store_data_aligned = '0; + write_strobe = 8'b0000_0000; + + // Mem address lower 3 bits determine the alignment within the 64-bit word + align_offset = mem_alu_result[2:0]; + + if (mem_is_store) begin + case (mem_mem_size) + // SB: Store Byte + 3'b000: begin + store_data_aligned = {56'b0, mem_rs2_rdata[7:0]} << (align_offset * 8); + write_strobe = 8'b0000_0001 << align_offset; + end + // SH: Store Halfword + 3'b001: begin + store_data_aligned = {48'b0, mem_rs2_rdata[15:0]} << (align_offset * 8); + write_strobe = 8'b0000_0011 << align_offset; + end + // SW: Store Word + 3'b010: begin + store_data_aligned = {32'b0, mem_rs2_rdata[31:0]} << (align_offset * 8); + write_strobe = 8'b0000_1111 << align_offset; + end + // SD: Store Doubleword + 3'b011: begin + store_data_aligned = mem_rs2_rdata; + write_strobe = 8'b1111_1111; + end + default: begin + store_data_aligned = '0; + write_strobe = 8'b0000_0000; + end + endcase + end + end + + assign dmem_wdata = store_data_aligned; + assign dmem_wstrb = write_strobe; + + // -------------------------- + // Load Data Alignment and Sign/Zero Extension + // -------------------------- + always_comb begin + logic [2:0] align_offset; + logic [XLEN-1:0] shifted_rdata; + load_data_aligned = '0; + + align_offset = mem_alu_result[2:0]; + + // Shift data down so the target bytes are at the bottom + shifted_rdata = dmem_rdata >> (align_offset * 8); + + case (mem_mem_size) + // LB: Load Byte (Sign extend) + 3'b000: load_data_aligned = { {56{shifted_rdata[7]}}, shifted_rdata[7:0] }; + // LH: Load Halfword (Sign extend) + 3'b001: load_data_aligned = { {48{shifted_rdata[15]}}, shifted_rdata[15:0] }; + // LW: Load Word (Sign extend) + 3'b010: load_data_aligned = { {32{shifted_rdata[31]}}, shifted_rdata[31:0] }; + // LD: Load Doubleword + 3'b011: load_data_aligned = shifted_rdata; + // LBU: Load Byte Unsigned (Zero extend) + 3'b100: load_data_aligned = { 56'b0, shifted_rdata[7:0] }; + // LHU: Load Half Unsigned (Zero extend) + 3'b101: load_data_aligned = { 48'b0, shifted_rdata[15:0] }; + // LWU: Load Word Unsigned (Zero extend) + 3'b110: load_data_aligned = { 32'b0, shifted_rdata[31:0] }; + default: load_data_aligned = '0; + endcase + end + + // -------------------------- + // Pass Output Signals to WB Stage + // -------------------------- + assign mem_wb_alu_result = mem_alu_result; + assign mem_wb_mem_rdata = load_data_aligned; + assign mem_wb_pc = mem_pc; + + assign mem_wb_reg_write_en = mem_reg_write_en; + assign mem_wb_rd_addr = mem_rd_addr; + assign mem_wb_wb_sel = mem_wb_sel; + + assign mem_wb_is_csr = mem_is_csr; + assign mem_wb_csr_op = mem_csr_op; + assign mem_wb_rs1_rdata = mem_rs1_rdata; + assign mem_wb_rs1_addr = mem_rs1_addr; + assign mem_wb_imm = mem_imm; + + assign mem_wb_illegal_instr = mem_illegal_instr; + assign mem_wb_is_ecall = mem_is_ecall; + assign mem_wb_is_ebreak = mem_is_ebreak; + assign mem_wb_is_mret = mem_is_mret; + assign mem_wb_is_sret = mem_is_sret; + +endmodule diff --git a/rv64cpu/rtl/core/mem_wb_reg.sv b/rv64cpu/rtl/core/mem_wb_reg.sv new file mode 100644 index 0000000..eca60bc --- /dev/null +++ b/rv64cpu/rtl/core/mem_wb_reg.sv @@ -0,0 +1,132 @@ +// Richard CPU +// Copyright (C) 2026 Richard Qin + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// File path: rtl/core/mem_wb_reg.sv +// Description: MEM/WB pipeline stage register (Memory Access to Write Back) +// Passes the final computation results, memory read data, and write-back control signals to the write-back stage + +module mem_wb_reg + import rv64_pkg::*; +( + input logic clk, + input logic rst, + + // ----------------------- + // Control Signals from Hazard Unit + input logic stall_en, + input logic flush_en, + + // ----------------------- + // Inputs from MEM stage + // ----------------------- + // Data and addresses + input logic [XLEN-1:0] mem_pc, + input logic [XLEN-1:0] mem_alu_result, + input logic [XLEN-1:0] mem_mem_rdata, + + // Write back control + input logic mem_reg_write_en, + input logic [4:0] mem_rd_addr, + input logic [1:0] mem_wb_sel, + + // CSR & System + input logic mem_is_csr, + input logic [2:0] mem_csr_op, + input logic [XLEN-1:0] mem_rs1_rdata, + input logic [4:0] mem_rs1_addr, + input logic [XLEN-1:0] mem_imm, + input logic mem_illegal_instr, + input logic mem_is_ecall, + input logic mem_is_ebreak, + input logic mem_is_mret, + input logic mem_is_sret, + + // ----------------------- + // Outputs to WB Stage + // ----------------------- + // Data and address + output logic [XLEN-1:0] wb_pc, + output logic [XLEN-1:0] wb_alu_result, + output logic [XLEN-1:0] wb_mem_rdata, + + // Write back control + output logic wb_reg_write_en, + output logic [4:0] wb_rd_addr, + output logic [1:0] wb_wb_sel, + + // CSR & System + output logic wb_is_csr, + output logic [2:0] wb_csr_op, + output logic [XLEN-1:0] wb_rs1_rdata, + output logic [4:0] wb_rs1_addr, + output logic [XLEN-1:0] wb_imm, + output logic wb_illegal_instr, + output logic wb_is_ecall, + output logic wb_is_ebreak, + output logic wb_is_mret, + output logic wb_is_sret + +); + // Sequential Logic: State Update + always_ff @(posedge clk) begin + if (rst) begin + wb_pc <= '0; + wb_alu_result <= '0; + wb_mem_rdata <= '0; + wb_reg_write_en <= '0; + wb_rd_addr <= '0; + wb_wb_sel <= '0; + wb_is_csr <= '0; + wb_csr_op <= '0; + wb_rs1_rdata <= '0; + wb_rs1_addr <= '0; + wb_imm <= '0; + wb_illegal_instr <= '0; + wb_is_ecall <= '0; + wb_is_ebreak <= '0; + wb_is_mret <= '0; + wb_is_sret <= '0; + end else if (flush_en) begin + // Target specific control signals to clear. Leave datapath elements intact + // to avoid extreme power consumption from massive flip-flop state changes array. + wb_reg_write_en <= '0; + wb_is_csr <= '0; + wb_illegal_instr <= '0; + wb_is_ecall <= '0; + wb_is_ebreak <= '0; + wb_is_mret <= '0; + wb_is_sret <= '0; + end else if (!stall_en) begin + wb_pc <= mem_pc; + wb_alu_result <= mem_alu_result; + wb_mem_rdata <= mem_mem_rdata; + wb_reg_write_en <= mem_reg_write_en; + wb_rd_addr <= mem_rd_addr; + wb_wb_sel <= mem_wb_sel; + wb_is_csr <= mem_is_csr; + wb_csr_op <= mem_csr_op; + wb_rs1_rdata <= mem_rs1_rdata; + wb_rs1_addr <= mem_rs1_addr; + wb_imm <= mem_imm; + wb_illegal_instr <= mem_illegal_instr; + wb_is_ecall <= mem_is_ecall; + wb_is_ebreak <= mem_is_ebreak; + wb_is_mret <= mem_is_mret; + wb_is_sret <= mem_is_sret; + end + end + +endmodule -- cgit v1.2.3