From f6441a2e6f901748b504ef93872649c9463a404e Mon Sep 17 00:00:00 2001
From: Richard Qin <richard.qin.x@gmail.com>
Date: Sun, 15 Mar 2026 16:07:39 +0800
Subject: initial commit: project architecture

---
 rv64cpu/scripts/gen_hex.sh | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100755 rv64cpu/scripts/gen_hex.sh

(limited to 'rv64cpu/scripts/gen_hex.sh')

diff --git a/rv64cpu/scripts/gen_hex.sh b/rv64cpu/scripts/gen_hex.sh
new file mode 100755
index 0000000..8ba4c94
--- /dev/null
+++ b/rv64cpu/scripts/gen_hex.sh
@@ -0,0 +1,25 @@
+#!/usr/bin/env bash
+# ─── gen_hex.sh ──────────────────────────────────────────────────────────────────
+# Convert an ELF file to Verilog hex format for $readmemh
+#
+# Usage: ./scripts/gen_hex.sh <input.elf> [output.hex]
+# ─────────────────────────────────────────────────────────────────────────────────
+set -euo pipefail
+
+CROSS_PREFIX="${CROSS_PREFIX:-riscv64-unknown-elf-}"
+
+if [ $# -lt 1 ]; then
+    echo "Usage: $0 <input.elf> [output.hex]"
+    exit 1
+fi
+
+INPUT="$1"
+OUTPUT="${2:-${INPUT%.elf}.hex}"
+
+${CROSS_PREFIX}objcopy -O verilog "$INPUT" "$OUTPUT"
+echo "[gen_hex] $INPUT → $OUTPUT"
+
+# Also generate .bin and disassembly for inspection
+${CROSS_PREFIX}objcopy -O binary "$INPUT" "${INPUT%.elf}.bin"
+${CROSS_PREFIX}objdump -d -M no-aliases "$INPUT" > "${INPUT%.elf}.dump"
+echo "[gen_hex] Also generated .bin and .dump"
-- 
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