From 149bf049d83d08e5d3a20862a3b894633e61c95b Mon Sep 17 00:00:00 2001
From: Richard Qin <richard.qin.x@gmail.com>
Date: Mon, 16 Mar 2026 19:52:33 +0800
Subject: Instruction fetching stage unit and test

---
 rv64cpu/tb/CMakeLists.txt | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'rv64cpu/tb/CMakeLists.txt')

diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt
index 4bafc67..8fc3ccf 100644
--- a/rv64cpu/tb/CMakeLists.txt
+++ b/rv64cpu/tb/CMakeLists.txt
@@ -65,6 +65,15 @@ add_verilator_target(
     INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
     TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_branch.cc
 )
+
+add_verilator_target(
+    NAME        tb_if_stage
+    TOP_MODULE  if_stage
+    SOURCES     ${RTL_CORE_DIR}/include/rv64_pkg.sv
+                ${RTL_CORE_DIR}/if_stage.sv
+    INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
+    TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_if_stage.cc
+)
 #
 # add_verilator_target(
 #     NAME        tb_csr
-- 
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