From 48489af495086d794f1b57bbb62ea1d8aca86ac5 Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Wed, 18 Mar 2026 03:09:38 +0800 Subject: CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit --- rv64cpu/tb/CMakeLists.txt | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) (limited to 'rv64cpu/tb/CMakeLists.txt') diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt index 11fb3fc..1b6173a 100644 --- a/rv64cpu/tb/CMakeLists.txt +++ b/rv64cpu/tb/CMakeLists.txt @@ -173,14 +173,30 @@ add_verilator_target( # ═══════════════════════════════════════════════════════════════════════════════════ # Core Integration Test # ═══════════════════════════════════════════════════════════════════════════════════ -# -# add_verilator_target( -# NAME tb_core -# TOP_MODULE richard_core -# SOURCES ${ALL_RTL_SOURCES} -# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} -# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/core/tb_core.cc -# ) + +add_verilator_target( + NAME tb_core + TOP_MODULE richard_core + SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv + ${RTL_CORE_DIR}/alu.sv + ${RTL_CORE_DIR}/branch_unit.sv + ${RTL_CORE_DIR}/decoder.sv + ${RTL_CORE_DIR}/regfile.sv + ${RTL_CORE_DIR}/if_stage.sv + ${RTL_CORE_DIR}/if_id_reg.sv + ${RTL_CORE_DIR}/id_stage.sv + ${RTL_CORE_DIR}/id_ex_reg.sv + ${RTL_CORE_DIR}/ex_stage.sv + ${RTL_CORE_DIR}/ex_mem_reg.sv + ${RTL_CORE_DIR}/mem_stage.sv + ${RTL_CORE_DIR}/mem_wb_reg.sv + ${RTL_CORE_DIR}/wb_stage.sv + ${RTL_CORE_DIR}/hazard_unit.sv + ${RTL_CORE_DIR}/richard_core.sv + INCLUDE_DIRS ${RTL_COMMON_INCLUDES} + TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/core/tb_core.cc + EXTRA_FLAGS -Wno-PINCONNECTEMPTY +) # ═══════════════════════════════════════════════════════════════════════════════════ # SoC Integration Test -- cgit v1.2.3