From 7c671e752160174965b8af8b66b9df15e00a4387 Mon Sep 17 00:00:00 2001
From: Richard Qin <richard.qin.x@gmail.com>
Date: Tue, 17 Mar 2026 01:02:51 +0800
Subject: Instruction Decoder Stage unit and tests

---
 rv64cpu/tb/CMakeLists.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'rv64cpu/tb/CMakeLists.txt')

diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt
index 8fc3ccf..78ab903 100644
--- a/rv64cpu/tb/CMakeLists.txt
+++ b/rv64cpu/tb/CMakeLists.txt
@@ -74,6 +74,17 @@ add_verilator_target(
     INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
     TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_if_stage.cc
 )
+
+add_verilator_target(
+    NAME        tb_id_stage
+    TOP_MODULE  id_stage
+    SOURCES     ${RTL_CORE_DIR}/include/rv64_pkg.sv
+                ${RTL_CORE_DIR}/decoder.sv
+                ${RTL_CORE_DIR}/regfile.sv
+                ${RTL_CORE_DIR}/id_stage.sv
+    INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
+    TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_id_stage.cc
+)
 #
 # add_verilator_target(
 #     NAME        tb_csr
-- 
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