From bd1d53990e8e7b94a2126682a3146de01a0c76ad Mon Sep 17 00:00:00 2001
From: Richard Qin <richard.qin.x@gmail.com>
Date: Wed, 18 Mar 2026 00:03:09 +0800
Subject: Memory Stage and MEM/WB pipeline stage register

---
 rv64cpu/tb/CMakeLists.txt | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'rv64cpu/tb/CMakeLists.txt')

diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt
index 67d3c7a..7ca5bf0 100644
--- a/rv64cpu/tb/CMakeLists.txt
+++ b/rv64cpu/tb/CMakeLists.txt
@@ -123,6 +123,24 @@ add_verilator_target(
     INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
     TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_ex_mem_reg.cc
 )
+
+add_verilator_target(
+    NAME        tb_mem_stage
+    TOP_MODULE  mem_stage
+    SOURCES     ${RTL_CORE_DIR}/include/rv64_pkg.sv
+                ${RTL_CORE_DIR}/mem_stage.sv
+    INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
+    TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_mem_stage.cc
+)
+
+add_verilator_target(
+    NAME        tb_mem_wb_reg
+    TOP_MODULE  mem_wb_reg
+    SOURCES     ${RTL_CORE_DIR}/include/rv64_pkg.sv
+                ${RTL_CORE_DIR}/mem_wb_reg.sv
+    INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
+    TB_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_mem_wb_reg.cc
+)
 #
 # add_verilator_target(
 #     NAME        tb_csr
-- 
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