From 48489af495086d794f1b57bbb62ea1d8aca86ac5 Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Wed, 18 Mar 2026 03:09:38 +0800 Subject: CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit --- rv64cpu/tb/unit/tb_hazard_unit.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'rv64cpu/tb/unit/tb_hazard_unit.cc') diff --git a/rv64cpu/tb/unit/tb_hazard_unit.cc b/rv64cpu/tb/unit/tb_hazard_unit.cc index 94dbeb6..69ebab9 100644 --- a/rv64cpu/tb/unit/tb_hazard_unit.cc +++ b/rv64cpu/tb/unit/tb_hazard_unit.cc @@ -1,5 +1,17 @@ // Richard CPU // Copyright (C) 2026 Richard Qin +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . // File path: tb/unit/tb_hazard_unit.cc // Description: Hazard Unit testbench — exhaustive forwarding, stall, and flush tests -- cgit v1.2.3