From 36ee7251fbb4350a5eee2549857e81291413e25d Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Sat, 7 Nov 2026 04:11:58 +0800 Subject: build: reorganize CMake configuration --- rv64cpu/CMakeLists.txt | 53 ++++++++++------------------------------------ rv64cpu/rtl/CMakeLists.txt | 44 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 42 deletions(-) create mode 100644 rv64cpu/rtl/CMakeLists.txt (limited to 'rv64cpu') diff --git a/rv64cpu/CMakeLists.txt b/rv64cpu/CMakeLists.txt index da146d5..f16aa14 100644 --- a/rv64cpu/CMakeLists.txt +++ b/rv64cpu/CMakeLists.txt @@ -4,35 +4,22 @@ if(POLICY CMP0144) cmake_policy(SET CMP0144 NEW) endif() -project(richard_cpu +project(rv64cpu VERSION 0.1.0 - DESCRIPTION "RV64IMAZicsr_Zifencei Five-Stage Pipelined CPU SoC" - LANGUAGES CXX C + DESCRIPTION "RV64 RISC-V processor core written in SystemVerilog" + LANGUAGES CXX ) set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_STANDARD_REQUIRED ON) set(CMAKE_EXPORT_COMPILE_COMMANDS ON) -# ─── Options ──────────────────────────────────────────────────────────────────── -option(ENABLE_TRACE "Enable VCD waveform tracing" ON) -option(ENABLE_COVERAGE "Enable code coverage for RTL" OFF) -option(BUILD_SW "Build software targets (requires riscv64 toolchain)" OFF) +option(ENABLE_TRACE "Enable VCD waveform tracing" OFF) +option(ENABLE_COVERAGE "Enable RTL code coverage" OFF) -# ─── Locate Verilator ──────────────────────────────────────────────────────────── find_package(verilator REQUIRED HINTS $ENV{VERILATOR_ROOT}) message(STATUS "Found Verilator: ${verilator_DIR}") -# ─── RTL Source Directories ────────────────────────────────────────────────────── -set(RTL_DIR ${CMAKE_SOURCE_DIR}/rtl) -set(RTL_CORE_DIR ${RTL_DIR}/core) -set(RTL_CACHE_DIR ${RTL_DIR}/cache) -set(RTL_BUS_DIR ${RTL_DIR}/bus) -set(RTL_PERIPS_DIR ${RTL_DIR}/perips) -set(RTL_SOC_DIR ${RTL_DIR}/soc) -set(RTL_INCLUDE_DIR ${RTL_CORE_DIR}/include) - -# ─── Common Verilator Flags ────────────────────────────────────────────────────── set(VERILATOR_COMMON_FLAGS --sv -Wall @@ -51,31 +38,13 @@ if(ENABLE_COVERAGE) list(APPEND VERILATOR_COMMON_FLAGS --coverage) endif() -# ─── Include Verilator CMake Helper ────────────────────────────────────────────── -include(${CMAKE_SOURCE_DIR}/tools/verilator.cmake) - -# ─── Waveform Output Directory ────────────────────────────────────────────────── -file(MAKE_DIRECTORY ${CMAKE_SOURCE_DIR}/waves) - -# ─── Testing ──────────────────────────────────────────────────────────────────── -enable_testing() -include(CTest) +include(${CMAKE_SOURCE_DIR}/cmake/verilator.cmake) -# ─── Testbench Subdirectory ───────────────────────────────────────────────────── -add_subdirectory(tb) - -# ─── Software Subdirectory (optional) ─────────────────────────────────────────── -if(BUILD_SW) - add_subdirectory(sw) -endif() +add_subdirectory(rtl) -# ─── Summary ──────────────────────────────────────────────────────────────────── message(STATUS "") -message(STATUS "╔══════════════════════════════════════════════╗") -message(STATUS "║ richard-cpu build configuration ║") -message(STATUS "╠══════════════════════════════════════════════╣") -message(STATUS "║ Trace: ${ENABLE_TRACE}") -message(STATUS "║ Coverage: ${ENABLE_COVERAGE}") -message(STATUS "║ Software: ${BUILD_SW}") -message(STATUS "╚══════════════════════════════════════════════╝") +message(STATUS "RV64CPU configuration") +message(STATUS " Trace: ${ENABLE_TRACE}") +message(STATUS " Coverage: ${ENABLE_COVERAGE}") +message(STATUS " RTL files: ${RV64CPU_RTL_SOURCE_COUNT}") message(STATUS "") diff --git a/rv64cpu/rtl/CMakeLists.txt b/rv64cpu/rtl/CMakeLists.txt new file mode 100644 index 0000000..96560fc --- /dev/null +++ b/rv64cpu/rtl/CMakeLists.txt @@ -0,0 +1,44 @@ +set(RV64CPU_RTL_SOURCES + ${CMAKE_CURRENT_SOURCE_DIR}/packages/rv64_pkg.sv + ${CMAKE_CURRENT_SOURCE_DIR}/packages/csr_pkg.sv + + ${CMAKE_CURRENT_SOURCE_DIR}/core/execute/integer_alu.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/execute/branch_unit.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/execute/instruction_decoder.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/execute/compressed_decoder.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/execute/hazard_unit.sv + + ${CMAKE_CURRENT_SOURCE_DIR}/core/registers/gpr_file.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/registers/fpr_file.sv + + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/if_stage.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/if_id_reg.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/id_stage.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/id_ex_reg.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/ex_stage.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/ex_mem_reg.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/mem_stage.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/mem_wb_reg.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/pipeline/wb_stage.sv + + ${CMAKE_CURRENT_SOURCE_DIR}/core/privileged/csr_unit.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/privileged/trap_controller.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/privileged/pmp_checker.sv + + ${CMAKE_CURRENT_SOURCE_DIR}/core/mmu/tlb.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/mmu/ptw.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/mmu/mmu.sv + + ${CMAKE_CURRENT_SOURCE_DIR}/core/fpu/fpu.sv + ${CMAKE_CURRENT_SOURCE_DIR}/core/rv64_core.sv +) + +set(RV64CPU_RTL_INCLUDE_DIRS + ${CMAKE_CURRENT_SOURCE_DIR}/packages +) + +list(LENGTH RV64CPU_RTL_SOURCES RV64CPU_RTL_SOURCE_COUNT) + +set(RV64CPU_RTL_SOURCES ${RV64CPU_RTL_SOURCES} PARENT_SCOPE) +set(RV64CPU_RTL_INCLUDE_DIRS ${RV64CPU_RTL_INCLUDE_DIRS} PARENT_SCOPE) +set(RV64CPU_RTL_SOURCE_COUNT ${RV64CPU_RTL_SOURCE_COUNT} PARENT_SCOPE) -- cgit v1.2.3