From def178f9df3819f01092400893651a148d529f2f Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Wed, 1 Apr 2026 05:11:48 +0800 Subject: docs: update README and ISA support matrix with new dependencies and compliance status --- rv64cpu/README.md | 27 ++++++++++++++++++++++----- rv64cpu/docs/isa_support.md | 40 ++++++++++++++++++++++++++++------------ 2 files changed, 50 insertions(+), 17 deletions(-) (limited to 'rv64cpu') diff --git a/rv64cpu/README.md b/rv64cpu/README.md index e2b767d..72b3546 100644 --- a/rv64cpu/README.md +++ b/rv64cpu/README.md @@ -24,6 +24,9 @@ Written in SystemVerilog, simulated with Verilator, targeting official riscv-arc - CMake ≥ 3.20 - C++17 compiler (GCC / Clang) - [riscv64-unknown-elf-gcc](https://github.com/riscv-collab/riscv-gnu-toolchain) (software compilation, optional) +- [uv](https://docs.astral.sh/uv/) (ACT4 Python tooling) +- [podman](https://podman.io/) (riscv-unified-db runtime) +- [sail_riscv_sim 0.10](https://github.com/riscv/sail-riscv/releases/tag/0.10) (reference model for ACT4) - [GTKWave](http://gtkwave.sourceforge.net/) (waveform viewer, optional) ### Build Simulation @@ -54,10 +57,24 @@ cmake --build build_sw -j$(nproc) # Initialize riscv-arch-test submodule git submodule update --init --recursive -# Run RV64I test suite -python3 scripts/run_compliance.py --suite rv64i -v +# Sync ACT4 python dependencies +cd sw/riscv-arch-test && uv sync --frozen && cd ../.. + +# Run strict full implemented suite (reference signature compare enabled) +python3 scripts/run_compliance.py --suite rv64full --max-cycles 200000 --require-reference ``` +Verified strict suites (all pass): + +- `rv64i` +- `rv64im` +- `rv64ia` +- `rv64ic` +- `rv64if` +- `rv64id` +- `rv64priv` +- `rv64full` (aggregate) + ### View Waveforms ```bash @@ -111,12 +128,12 @@ richard-cpu/ | Phase | Milestone | |---|---| -| P1 | RV64I five-stage pipeline + hazard handling | -| P2 | CSR + M/S/U privilege levels + Trap | +| P1 | RV64I five-stage pipeline + hazard handling (Done) | +| P2 | CSR + M/S/U privilege levels + Trap (Done) | | P3 | MMU (Sv39 TLB + PTW) | | P4 | Cache + AXI4-Full Burst | | P5 | Peripherals + AXI4-Lite bridge + SoC integration | -| P6 | Pass riscv-arch-test | +| P6 | Pass riscv-arch-test (In Progress: strict suites above all pass) | | P7 | M/F/D/A/C extensions + FPGA bring-up | ## License diff --git a/rv64cpu/docs/isa_support.md b/rv64cpu/docs/isa_support.md index cf8c9c4..0173a58 100644 --- a/rv64cpu/docs/isa_support.md +++ b/rv64cpu/docs/isa_support.md @@ -14,22 +14,38 @@ Equivalent to `RV64IMAFDCZicsr_Zifencei` | Extension | Full Name | Status | Description | |---|---|---|---| -| **I** | Base Integer (RV64I) | 🟡 In progress | Five-stage RV64I pipeline, ALU, and branch unit implemented and covered by unit tests ([rtl/core/alu.sv](rtl/core/alu.sv), [tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)) | -| **M** | Multiply/Divide | 🔴 Not implemented | Multiply, divide, remainder | -| **A** | Atomic | 🔴 Not implemented | LR/SC, AMO atomic instructions | -| **F** | Single-Precision Float | 🔴 Not implemented | 32-bit IEEE 754 floating-point | -| **D** | Double-Precision Float | 🔴 Not implemented | 64-bit IEEE 754 floating-point | -| **C** | Compressed | 🔴 Not implemented | 16-bit compressed instructions | +| **I** | Base Integer (RV64I) | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64i`) | +| **M** | Multiply/Divide | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64im`) | +| **A** | Atomic | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64ia`) | +| **F** | Single-Precision Float | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64if`) | +| **D** | Double-Precision Float | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64id`) | +| **C** | Compressed | 🟢 Implemented | Strict ACT4 compliance suite passes (`rv64ic`) | | **Zicsr** | CSR Instructions | 🟢 Implemented | Full CSR unit with delegation, FCSR, and dedicated testbench ([rtl/core/csr_unit.sv](rtl/core/csr_unit.sv), [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc)) | -| **Zifencei** | Instruction Fence | 🟡 Decoding only | Decoder recognizes FENCE.I; cache invalidation hookup pending | +| **Zifencei** | Instruction Fence | 🟢 Implemented | Included in strict ACT4 passing suites | ---- +Privilege-related tests (`S`, `Sm`) also pass through `rv64priv` strict suite. -## Recent Progress Highlights (2026-03) +--- -- **CSR subsystem**: `csr_unit` now handles delegation, privilege transitions, and floating-point CSRs, verified by [tb/unit/tb_csr.cc](tb/unit/tb_csr.cc). -- **Integer execution path**: ALU, branch, and decode paths for RV64I arithmetic/logic instructions are implemented with passing unit tests ([tb/unit/tb_alu.cc](tb/unit/tb_alu.cc), [tb/unit/tb_branch.cc](tb/unit/tb_branch.cc)). -- **Decoder coverage**: Load/store, immediate, and system opcode paths exist with clear TODO markers for upcoming M/A/F extensions, see [rtl/core/decoder.sv](rtl/core/decoder.sv). +## Recent Progress Highlights (2026-04) + +- `riscv-arch-test` ACT4 flow integrated in `scripts/run_compliance.py`. +- Dedicated `tb/compliance/compliance_runner.cc` executes ELF tests and dumps signatures. +- Strict suite passes with reference comparison enabled (`--require-reference`): + - `rv64i` (51/51) + - `rv64im` (64/64) + - `rv64ia` (51/51) + - `rv64ic` (51/51) + - `rv64if` (133/133) + - `rv64id` (165/165) + - `rv64priv` (2/2) + - `rv64full` aggregate (262/262) + +## Detailed Instruction Tables + +The detailed per-instruction checklist sections below are retained as reference, +but are not the primary source of truth for completion status at this stage. +Current completion is determined by strict ACT4 suite pass results listed above. --- -- cgit v1.2.3