feat: Add initial Supervisor Mode Trap Handler

Implement the initial mechanism for handling traps and exceptions in Supervisor Mode.

Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point.

Implemented assembly code for saving and restoring the Trap Context (register state).

Provides the foundational framework necessary for future Timer Interrupts and System Calls.

1 files changed, 0 insertions, 0 deletions

diff --git a/build/kernel.elf b/build/kernel.elf
index 6e2868c..9b56c35 100755
--- a/build/kernel.elf
+++ b/build/kernel.elf