feat: establish bootable new architecture checkpoint

Replace the compressed boot path with a relocatable higher-half RISC-V entry, expand memory and SMP support, and add the driver, TTY, VFS, exec, signal, syscall, initramfs, and self-test infrastructure needed for a bootable kernel checkpoint.

1 files changed, 9 insertions, 1 deletions

diff --git a/na/arch/riscv/trap/trap_vector.S b/na/arch/riscv/trap/trap_vector.S
index 160b122..8e45cae 100644
--- a/na/arch/riscv/trap/trap_vector.S
+++ b/na/arch/riscv/trap/trap_vector.S
@@ -90,6 +90,15 @@ trap_vector:
     /* Step 6: flush TLB after page table switch */
     sfence.vma zero, zero
 
+    /* Step 6.5: restore kernel gp (global pointer).
+     * The compiler uses gp-relative addressing for global variable access
+     * (e.g. ld reg, offset(gp)).  User mode may have set gp to anything,
+     * so we MUST reload it before entering any C++ code. */
+.option push
+.option norelax
+    la gp, __global_pointer$
+.option pop
+
     /* Pass TrapFrame* to C++ handler (a0 = tf) */
     mv a0, tp
 
@@ -97,7 +106,6 @@ trap_vector:
     mv tp, t2
 
     /* Step 7: jump to C++ trap_handler */
-    /* Step 7: jump to C++ trap_handler */
     jalr t3