feat: implement hardware random number generation and early PRNG initialization

2 files changed, 48 insertions, 0 deletions

diff --git a/na/arch/riscv/include/arch/random.h b/na/arch/riscv/include/arch/random.h
new file mode 100644
index 0000000..8c8c051
--- /dev/null
+++ b/na/arch/riscv/include/arch/random.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2026 Richard Qin */
+
+#pragma once
+
+#include <lume/types.h>
+
+namespace arch {
+
+/*
+ * Get a random 64-bit value from the hardware TRNG.
+ * Returns true if supported and successful, false otherwise.
+ */
+bool get_hw_random(uint64& value);
+
+/*
+ * Get the current high-resolution hardware cycle counter.
+ * Used as an entropy fallback (Jitter/Timer).
+ */
+inline uint64 get_cycles()
+{
+    uint64 cycles;
+    __asm__ volatile("rdcycle %0" : "=r"(cycles));
+    return cycles;
+}
+
+} // namespace arch
diff --git a/na/arch/riscv/lib/random.cc b/na/arch/riscv/lib/random.cc
new file mode 100644
index 0000000..afc0078
--- /dev/null
+++ b/na/arch/riscv/lib/random.cc
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2026 Richard Qin */
+
+#include <arch/random.h>
+#include <lume/klog.h>
+
+namespace arch {
+
+bool get_hw_random(uint64& value)
+{
+    /*
+     * Real implementation would check for Zkr extension and execute:
+     *   csrr x, seed
+     * 
+     * Since QEMU virt doesn't guarantee Zkr, we return false to
+     * force the MI layer to use the timer fallback.
+     */
+    return false;
+}
+
+} // namespace arch