feat: establish bootable new architecture checkpoint

Replace the compressed boot path with a relocatable higher-half RISC-V entry, expand memory and SMP support, and add the driver, TTY, VFS, exec, signal, syscall, initramfs, and self-test infrastructure needed for a bootable kernel checkpoint.

1 files changed, 10 insertions, 1 deletions

diff --git a/na/kernel/sync/spinlock.cc b/na/kernel/sync/spinlock.cc
index bca4684..f649fe7 100644
--- a/na/kernel/sync/spinlock.cc
+++ b/na/kernel/sync/spinlock.cc
@@ -17,6 +17,7 @@
 #include "cpu_state.h"
 #include <arch/cpu.h>
 #include <lume/klog.h>
+#include <lume/task.h>
 
 // ============================================================
 // Per-CPU sync state (BSS zero-initialized)
@@ -88,6 +89,10 @@ void Spinlock::acquire() {
 
     // Step 4: record owner
     cpu_id_ = arch::cpu::id();
+
+    // Step 5: bump preempt_count — prevents schedule() from preempting
+    TaskControlBlock* curr = current_task();
+    if (curr) curr->preempt_count++;
 }
 
 void Spinlock::release() {
@@ -102,7 +107,11 @@ void Spinlock::release() {
     // Step 3: release the lock with release semantics
     locked_.store(0, __ATOMIC_RELEASE);
 
-    // Step 4: restore interrupt state if this was the last lock
+    // Step 4: drop preempt_count
+    TaskControlBlock* curr = current_task();
+    if (curr) curr->preempt_count--;
+
+    // Step 5: restore interrupt state if this was the last lock
     sync::pop_intr();
 }