feat: implement FDT-based memory discovery and add comprehensive debug logging to exec syscalls

1 files changed, 27 insertions, 13 deletions

diff --git a/src/drivers/plic.cc b/src/drivers/plic.cc
index f9e306b..a975c44 100644
--- a/src/drivers/plic.cc
+++ b/src/drivers/plic.cc
@@ -1,18 +1,18 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright (C) 2026 Richard QIn
+ * Copyright (C) 2026 Richard Qin
  */
 #include "common/types.h"
 #include "kernel/riscv.h"
 #include "drivers/plic.h"
 #include "drivers/uart.h"
+#include "kernel/fdt.h"
 
-// Base Constants
-constexpr uint64 PLIC_BASE = 0x0c000000L;
-constexpr uint64 PLIC_PRIORITY = PLIC_BASE + 0x0;
-constexpr uint64 PLIC_PENDING = PLIC_BASE + 0x1000;
+// Helper Macros — all relative to PLIC base from FDT
+#define PLIC_BASE      (g_devices.plic.base_addr)
+#define PLIC_PRIORITY  (PLIC_BASE + 0x0)
+#define PLIC_PENDING   (PLIC_BASE + 0x1000)
 
-// Helper Macros to calculate addresses
 #define PLIC_SENABLE_ADDR(hart) (PLIC_BASE + 0x2080 + (hart) * 0x100)
 #define PLIC_STHRESHOLD_ADDR(hart) (PLIC_BASE + 0x201000 + (hart) * 0x2000)
 #define PLIC_SCLAIM_ADDR(hart) (PLIC_BASE + 0x201004 + (hart) * 0x2000)
@@ -27,12 +27,15 @@ namespace PLIC
 {
     void init()
     {
-        // Set Priority for UART (IRQ 10) and VirtIO (IRQ 1)
-        // Must use volatile write
-        *REG32(PLIC_PRIORITY + 10 * 4) = 1;
-        for (int i = 1; i <= 8; i++)
+        // Set priority for UART IRQ
+        if (g_devices.uart.irq > 0)
+            *REG32(PLIC_PRIORITY + g_devices.uart.irq * 4) = 1;
+
+        // Set priority for all VirtIO IRQs
+        for (int i = 0; i < g_devices.virtio_count; i++)
         {
-            *REG32(PLIC_PRIORITY + i * 4) = 1;
+            if (g_devices.virtio[i].irq > 0)
+                *REG32(PLIC_PRIORITY + g_devices.virtio[i].irq * 4) = 1;
         }
     }
 
@@ -40,8 +43,19 @@ namespace PLIC
     {
         int hart = static_cast<int>(r_tp());
 
-        // Enable UART(10) and VirtIO(1) for this Hart (S-Mode)
-        *REG32(PLIC_SENABLE_ADDR(hart)) = (1 << 10) | 0x1FE;
+        // Build enable bitmask from discovered devices
+        uint32 enable = 0;
+
+        if (g_devices.uart.irq > 0 && g_devices.uart.irq < 32)
+            enable |= (1 << g_devices.uart.irq);
+
+        for (int i = 0; i < g_devices.virtio_count; i++)
+        {
+            if (g_devices.virtio[i].irq > 0 && g_devices.virtio[i].irq < 32)
+                enable |= (1 << g_devices.virtio[i].irq);
+        }
+
+        *REG32(PLIC_SENABLE_ADDR(hart)) = enable;
 
         // Set Priority Threshold to 0 (Allow all)
         *REG32(PLIC_STHRESHOLD_ADDR(hart)) = 0;