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| author | Richard Qin <richard.qin.x@gmail.com> | 2025-12-10 01:19:32 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2025-12-10 01:19:32 +0800 |
| commit | 497e4a1b2f6f9181518e9887991c0464bd8f6bcf (patch) | |
| tree | efd498dd66b8995a4bd0e31ca6af454b4ef342d2 /src/kernel/trap/trap.S | |
| parent | c36e1b5e5e069ce1735dcc2a94aa45ba72ea2441 (diff) | |
| download | lume-497e4a1b2f6f9181518e9887991c0464bd8f6bcf.tar.gz lume-497e4a1b2f6f9181518e9887991c0464bd8f6bcf.tar.xz | |
feat: Add initial Supervisor Mode Trap Handler
Implement the initial mechanism for handling traps and exceptions in Supervisor Mode.
Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point.
Implemented assembly code for saving and restoring the Trap Context (register state).
Provides the foundational framework necessary for future Timer Interrupts and System Calls.
Diffstat (limited to 'src/kernel/trap/trap.S')
| -rw-r--r-- | src/kernel/trap/trap.S | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/src/kernel/trap/trap.S b/src/kernel/trap/trap.S new file mode 100644 index 0000000..ffce52a --- /dev/null +++ b/src/kernel/trap/trap.S @@ -0,0 +1,87 @@ +.section .text +.global kernelvec +.align 4 + +kernelvec: + + addi sp, sp, -256 + + sd ra, 40(sp) + sd sp, 48(sp) + sd gp, 56(sp) + sd tp, 64(sp) + sd t0, 72(sp) + sd t1, 80(sp) + sd t2, 88(sp) + sd s0, 96(sp) + sd s1, 104(sp) + sd a0, 112(sp) + sd a1, 120(sp) + sd a2, 128(sp) + sd a3, 136(sp) + sd a4, 144(sp) + sd a5, 152(sp) + sd a6, 160(sp) + sd a7, 168(sp) + sd s2, 176(sp) + sd s3, 184(sp) + sd s4, 192(sp) + sd s5, 200(sp) + sd s6, 208(sp) + sd s7, 216(sp) + sd s8, 224(sp) + sd s9, 232(sp) + sd s10, 240(sp) + sd s11, 248(sp) + sd t3, 256(sp) + sd t4, 264(sp) + sd t5, 272(sp) + sd t6, 280(sp) + + csrr t0, sepc + csrr t1, sstatus + sd t0, 24(sp) # Trapframe.epc + sd t1, 32(sp) # Trapframe.kernel_hartid + + mv a0, sp + call kerneltrap + + ld t0, 24(sp) + ld t1, 32(sp) + csrw sepc, t0 + csrw sstatus, t1 + + ld ra, 40(sp) + ld gp, 56(sp) + ld tp, 64(sp) + ld t0, 72(sp) + ld t1, 80(sp) + ld t2, 88(sp) + ld s0, 96(sp) + ld s1, 104(sp) + ld a0, 112(sp) + ld a1, 120(sp) + ld a2, 128(sp) + ld a3, 136(sp) + ld a4, 144(sp) + ld a5, 152(sp) + ld a6, 160(sp) + ld a7, 168(sp) + ld s2, 176(sp) + ld s3, 184(sp) + ld s4, 192(sp) + ld s5, 200(sp) + ld s6, 208(sp) + ld s7, 216(sp) + ld s8, 224(sp) + ld s9, 232(sp) + ld s10, 240(sp) + ld s11, 248(sp) + ld t3, 256(sp) + ld t4, 264(sp) + ld t5, 272(sp) + ld t6, 280(sp) + + addi sp, sp, 256 + + sret
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