| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | dev(device): implement VirtIO | Richard Qin | 2026-01-01 | 1 | -0/+0 |
| | | | | | See dev log for detail | ||||
| * | dev: PILC implementation | Richard Qin | 2025-12-31 | 1 | -0/+0 |
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| * | dev:Refactor Memory Management and Process Management | Richard Qin | 2025-12-31 | 1 | -0/+0 |
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| * | feat(syscall): Implement syscall dispatch and process lifecycle ↵ | Richard Qin | 2025-12-28 | 1 | -0/+0 |
| | | | | | (exit/wait/sleep) | ||||
| * | feat: Implement the first user program of the lume OS | Richard Qin | 2025-12-27 | 1 | -0/+0 |
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| * | feat: add preemptive scheduling, SBI timer support and FDT parser. | Richard Qin | 2025-12-13 | 1 | -0/+0 |
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| * | feat:Cooperative Multitasking | Richard Qin | 2025-12-11 | 1 | -0/+0 |
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| * | feat: Add initial Supervisor Mode Trap Handler | Richard Qin | 2025-12-10 | 1 | -0/+0 |
| Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls. | |||||
