blob: a759597a4e58750e5e4f2a0a90197dc95acd616e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
#include "common/types.h"
#include "kernel/riscv.h"
#include "drivers/plic.h"
#include "drivers/uart.h"
// Base Constants
constexpr uint64 PLIC_BASE = 0x0c000000L;
constexpr uint64 PLIC_PRIORITY = PLIC_BASE + 0x0;
constexpr uint64 PLIC_PENDING = PLIC_BASE + 0x1000;
// Helper Macros to calculate addresses
#define PLIC_SENABLE_ADDR(hart) (PLIC_BASE + 0x2080 + (hart) * 0x100)
#define PLIC_STHRESHOLD_ADDR(hart) (PLIC_BASE + 0x201000 + (hart) * 0x2000)
#define PLIC_SCLAIM_ADDR(hart) (PLIC_BASE + 0x201004 + (hart) * 0x2000)
// Helper for Volatile Access
static inline volatile uint32 *REG32(uint64 addr)
{
return reinterpret_cast<volatile uint32 *>(addr);
}
namespace PLIC
{
void init()
{
// Set Priority for UART (IRQ 10) and VirtIO (IRQ 1)
// Must use volatile write
*REG32(PLIC_PRIORITY + 10 * 4) = 1;
for (int i = 1; i <= 8; i++)
{
*REG32(PLIC_PRIORITY + i * 4) = 1;
}
}
void inithart()
{
int hart = static_cast<int>(r_tp());
// Enable UART(10) and VirtIO(1) for this Hart (S-Mode)
*REG32(PLIC_SENABLE_ADDR(hart)) = (1 << 10) | 0x1FE;
// Set Priority Threshold to 0 (Allow all)
*REG32(PLIC_STHRESHOLD_ADDR(hart)) = 0;
Drivers::uart_puts("[PLIC] Hart Init Done.\n");
}
int claim()
{
int hart = static_cast<int>(r_tp());
return *REG32(PLIC_SCLAIM_ADDR(hart));
}
void complete(int irq)
{
int hart = static_cast<int>(r_tp());
*REG32(PLIC_SCLAIM_ADDR(hart)) = static_cast<uint32>(irq);
}
}
|
