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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-04-01 02:35:21 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-04-01 05:02:48 +0800 |
| commit | 15fa51f04bf85239b26fe5bfb424aa38ce2fb888 (patch) | |
| tree | c5d43c013ce2944890718a217c347663b2acc0cc | |
| parent | 1f9f63fea8a6696a35c413b14efc74833f4140ed (diff) | |
| download | rcc-project-15fa51f04bf85239b26fe5bfb424aa38ce2fb888.tar.gz rcc-project-15fa51f04bf85239b26fe5bfb424aa38ce2fb888.tar.xz | |
feat: Add riscv-arch-test submodule for RISC-V architecture testing
| -rw-r--r-- | rv64cpu/.gitmodules | 3 | ||||
| m--------- | sw/riscv-arch-test | 0 |
2 files changed, 3 insertions, 0 deletions
diff --git a/rv64cpu/.gitmodules b/rv64cpu/.gitmodules new file mode 100644 index 0000000..33d2491 --- /dev/null +++ b/rv64cpu/.gitmodules @@ -0,0 +1,3 @@ +[submodule "sw/riscv-arch-test"] + path = sw/riscv-arch-test + url = https://github.com/riscv-non-isa/riscv-arch-test.git diff --git a/sw/riscv-arch-test b/sw/riscv-arch-test new file mode 160000 +Subproject b27b0cd9e00a35b267cebd9a0ce2a6445bc47d6 |