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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 02:39:11 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 02:39:11 +0800 |
| commit | 46db486c089e9c2d6b05287476d7975723929acf (patch) | |
| tree | 922b87bc316cbc151dda94f4eaa23ec23d3e2547 | |
| parent | 705ebca5d37ee30e9cd517fed5f09dbf12113e6b (diff) | |
| download | rcc-project-46db486c089e9c2d6b05287476d7975723929acf.tar.gz rcc-project-46db486c089e9c2d6b05287476d7975723929acf.tar.xz | |
[RISCV] Make call-preserved masks optional
| -rw-r--r-- | backend/lib/Target/RISCV/RISCV.rccdesc | 4 | ||||
| -rw-r--r-- | backend/unittests/Target/RISCVTargetTest.cpp | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc index 54372ea..bbf70b7 100644 --- a/backend/lib/Target/RISCV/RISCV.rccdesc +++ b/backend/lib/Target/RISCV/RISCV.rccdesc @@ -3643,7 +3643,7 @@ instructions: name: PseudoCALL operands: - { kinds: [global_symbol, external_symbol, register], role: use, allowed_target_flags: 1 } - - { kinds: [register_mask] } + - { kinds: [register_mask], optional: true } num_explicit_defs: 0 implicit_defs: [{ register: X1 }] allow_extra_implicit_operands: true @@ -3656,7 +3656,7 @@ instructions: name: PseudoTAIL operands: - { kinds: [global_symbol, external_symbol, register], role: use, allowed_target_flags: 1 } - - { kinds: [register_mask] } + - { kinds: [register_mask], optional: true } num_explicit_defs: 0 allow_extra_implicit_operands: true flags: [pseudo, produces_code, allowed_pre_legalizer, terminator, branch, call, barrier, may_load, may_store, has_side_effects, not_duplicable, unmodeled_side_effects] diff --git a/backend/unittests/Target/RISCVTargetTest.cpp b/backend/unittests/Target/RISCVTargetTest.cpp index 2515201..555db4c 100644 --- a/backend/unittests/Target/RISCVTargetTest.cpp +++ b/backend/unittests/Target/RISCVTargetTest.cpp @@ -188,6 +188,8 @@ void testInstructionFacts(TestContext &Context) { const auto *GenericAdd = Target->instructionDescriptor(rcc::opcode(rcc::GenericOpcode::G_ADD)); const auto *PseudoCall = Target->instructionDescriptor(rcc::Opcode::fromValue( static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::PseudoCALL))); + const auto *PseudoTail = Target->instructionDescriptor(rcc::Opcode::fromValue( + static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::PseudoTAIL))); const auto *Assembly = rcc::riscv::assemblyInstruction( rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::ADDI))); const auto *FenceAssembly = rcc::riscv::assemblyInstruction( @@ -239,7 +241,9 @@ void testInstructionFacts(TestContext &Context) { Compressed != nullptr && Compressed->ImplicitDefs.size() == 1 && Compressed->ImplicitUses.size() == 1 && GenericAdd != nullptr && GenericAdd->Flags.has(rcc::InstructionFlag::Generic) && PseudoCall != nullptr && - PseudoCall->Flags.has(rcc::InstructionFlag::Pseudo) && + PseudoCall->Operands.size() == 2 && PseudoCall->Operands[1].Optional && + PseudoTail != nullptr && PseudoTail->Operands.size() == 2 && + PseudoTail->Operands[1].Optional && PseudoCall->Flags.has(rcc::InstructionFlag::Pseudo) && PseudoCall->Flags.has(rcc::InstructionFlag::Call) && rcc::riscv::assemblyInstruction(PseudoCall->InstructionOpcode) == nullptr && Assembly != nullptr && Assembly->Mnemonic == "addi" && |