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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 03:14:46 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 03:14:46 +0800 |
| commit | 6f57dd79572c177b775a934bee54ceb85a55c28a (patch) | |
| tree | b0b26bbbe8d424730afcd437cb5a2220b1fd8542 | |
| parent | 1410d3309ae9557ab102942bbc4d8449f2206fe5 (diff) | |
| download | rcc-project-6f57dd79572c177b775a934bee54ceb85a55c28a.tar.gz rcc-project-6f57dd79572c177b775a934bee54ceb85a55c28a.tar.xz | |
refactor: rename RTL source files
| -rw-r--r-- | rv64cpu/rtl/core/execute/instruction_decoder.sv (renamed from rv64cpu/rtl/core/execute/decoder.sv) | 0 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/execute/integer_alu.sv (renamed from rv64cpu/rtl/core/execute/alu.sv) | 0 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/fpu/fpu.sv (renamed from rv64cpu/rtl/core/fpu/fpu_unit.sv) | 0 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/mmu/mmu.sv (renamed from rv64cpu/rtl/core/mmu/mmu_top.sv) | 0 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/privileged/trap_controller.sv (renamed from rv64cpu/rtl/core/privileged/trap_ctrl.sv) | 0 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/registers/fpr_file.sv (renamed from rv64cpu/rtl/core/registers/fp_regfile.sv) | 0 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/registers/gpr_file.sv (renamed from rv64cpu/rtl/core/registers/regfile.sv) | 0 | ||||
| -rw-r--r-- | rv64cpu/rtl/core/rv64_core.sv (renamed from rv64cpu/rtl/core/richard_core.sv) | 0 |
8 files changed, 0 insertions, 0 deletions
diff --git a/rv64cpu/rtl/core/execute/decoder.sv b/rv64cpu/rtl/core/execute/instruction_decoder.sv index c39a637..c39a637 100644 --- a/rv64cpu/rtl/core/execute/decoder.sv +++ b/rv64cpu/rtl/core/execute/instruction_decoder.sv diff --git a/rv64cpu/rtl/core/execute/alu.sv b/rv64cpu/rtl/core/execute/integer_alu.sv index 08635ce..08635ce 100644 --- a/rv64cpu/rtl/core/execute/alu.sv +++ b/rv64cpu/rtl/core/execute/integer_alu.sv diff --git a/rv64cpu/rtl/core/fpu/fpu_unit.sv b/rv64cpu/rtl/core/fpu/fpu.sv index a1962e1..a1962e1 100644 --- a/rv64cpu/rtl/core/fpu/fpu_unit.sv +++ b/rv64cpu/rtl/core/fpu/fpu.sv diff --git a/rv64cpu/rtl/core/mmu/mmu_top.sv b/rv64cpu/rtl/core/mmu/mmu.sv index 169bf81..169bf81 100644 --- a/rv64cpu/rtl/core/mmu/mmu_top.sv +++ b/rv64cpu/rtl/core/mmu/mmu.sv diff --git a/rv64cpu/rtl/core/privileged/trap_ctrl.sv b/rv64cpu/rtl/core/privileged/trap_controller.sv index 0969fdc..0969fdc 100644 --- a/rv64cpu/rtl/core/privileged/trap_ctrl.sv +++ b/rv64cpu/rtl/core/privileged/trap_controller.sv diff --git a/rv64cpu/rtl/core/registers/fp_regfile.sv b/rv64cpu/rtl/core/registers/fpr_file.sv index 67e83f9..67e83f9 100644 --- a/rv64cpu/rtl/core/registers/fp_regfile.sv +++ b/rv64cpu/rtl/core/registers/fpr_file.sv diff --git a/rv64cpu/rtl/core/registers/regfile.sv b/rv64cpu/rtl/core/registers/gpr_file.sv index dbc3c04..dbc3c04 100644 --- a/rv64cpu/rtl/core/registers/regfile.sv +++ b/rv64cpu/rtl/core/registers/gpr_file.sv diff --git a/rv64cpu/rtl/core/richard_core.sv b/rv64cpu/rtl/core/rv64_core.sv index 51c64f8..51c64f8 100644 --- a/rv64cpu/rtl/core/richard_core.sv +++ b/rv64cpu/rtl/core/rv64_core.sv |