[MIR] Accept empty optional register fields

3 files changed, 20 insertions, 9 deletions

diff --git a/backend/lib/MIR/MIRFrameParser.cpp b/backend/lib/MIR/MIRFrameParser.cpp
index 9e21dfc..176bf25 100644
--- a/backend/lib/MIR/MIRFrameParser.cpp
+++ b/backend/lib/MIR/MIRFrameParser.cpp
@@ -168,10 +168,15 @@ bool MIRDocumentParser::parseStackObjects(const yaml::Node &Root, MachineFunctio
           return true;
       }
       if (const yaml::Node *SavedNode = mappingValue(*Element, "callee-saved-register")) {
-        PhysicalRegister Reg;
-        if (physicalRegister(*SavedNode, Reg))
+        std::string_view SavedName;
+        if (scalar(*SavedNode, SavedName, "physical register"))
           return true;
-        Description.CalleeSavedRegister = Reg;
+        if (!trim(SavedName).empty()) {
+          PhysicalRegister Reg;
+          if (physicalRegister(SavedName, SavedNode->range(), Reg))
+            return true;
+          Description.CalleeSavedRegister = Reg;
+        }
       }
       if (const yaml::Node *RestoredNode = mappingValue(*Element, "callee-saved-restored")) {
         if (boolean(*RestoredNode, Description.CalleeSavedRestored))
diff --git a/backend/lib/MIR/MIRFunctionParser.cpp b/backend/lib/MIR/MIRFunctionParser.cpp
index a59e4bd..68bc0aa 100644
--- a/backend/lib/MIR/MIRFunctionParser.cpp
+++ b/backend/lib/MIR/MIRFunctionParser.cpp
@@ -285,12 +285,17 @@ bool MIRDocumentParser::parseRegisters(const yaml::Node &Root, MachineFunction &
       }
 
       if (const yaml::Node *Preferred = mappingValue(*Element, "preferred-register")) {
+        std::string_view PreferredName;
         PhysicalRegister Reg;
-        if (physicalRegister(*Preferred, Reg))
+        if (scalar(*Preferred, PreferredName, "physical register"))
           return true;
-        auto AddResult = Function.registerInfo().addAllocationHint(*Created, Reg);
-        if (!AddResult)
-          return importError(Preferred->range(), AddResult.error());
+        if (!trim(PreferredName).empty()) {
+          if (physicalRegister(PreferredName, Preferred->range(), Reg))
+            return true;
+          auto AddResult = Function.registerInfo().addAllocationHint(*Created, Reg);
+          if (!AddResult)
+            return importError(Preferred->range(), AddResult.error());
+        }
       }
       if (const yaml::Node *Flags = mappingValue(*Element, "flags")) {
         if (requireKind(*Flags, yaml::NodeKind::Sequence, "virtual-register flags"))
diff --git a/backend/unittests/MIR/MIRDocumentTest.cpp b/backend/unittests/MIR/MIRDocumentTest.cpp
index b6ca0bb..7192398 100644
--- a/backend/unittests/MIR/MIRDocumentTest.cpp
+++ b/backend/unittests/MIR/MIRDocumentTest.cpp
@@ -328,6 +328,7 @@ isSSA: true
 noVRegs: false
 registers:
   - { id: 7, class: gpr64, preferred-register: '$g1', flags: [ test-vreg-one ] }
+  - { id: 8, class: gpr64, preferred-register: '' }
 liveins:
   - { reg: '$g0', virtual-reg: '%7' }
 calleeSavedRegisters: [ '$g1' ]
@@ -346,7 +347,7 @@ frameInfo:
 fixedStack:
   - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8 }
 stack:
-  - { id: 4, name: slot, size: 8, alignment: 8, local-offset: 0,
+  - { id: 4, name: slot, size: 8, alignment: 8, callee-saved-register: '', local-offset: 0,
       debug-info-variable: '!0',
       debug-info-expression: '!DIExpression(DW_OP_LLVM_arg, 0, 18446744073709551615)',
       debug-info-location: '!DILocation(line: 4, column: 2, scope: !1, isImplicitCode: true)' }
@@ -426,7 +427,7 @@ void testDocumentTransaction(TestContext &Context) {
   if (Function == nullptr)
     return;
 
-  Context.expect(Function->registerInfo().virtualRegisters().size() == 1 &&
+  Context.expect(Function->registerInfo().virtualRegisters().size() == 2 &&
                      Function->registerInfo().liveIns().size() == 1 &&
                      Function->records().hasCalleeSavedRegisters(),
                  "register tables must publish into the common MachineIR model");