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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-15 01:34:21 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-15 01:34:21 +0800 |
| commit | c8bad4713f17c3624a6044885ee43d316953b598 (patch) | |
| tree | 0de398bc710f725c672dd679d32616f14eb7e247 | |
| parent | dc6ea141a331774f2ac3e10152cb690d6d3d3ca7 (diff) | |
| download | rcc-project-c8bad4713f17c3624a6044885ee43d316953b598.tar.gz rcc-project-c8bad4713f17c3624a6044885ee43d316953b598.tar.xz | |
[MIR] Print target generic operand types
Use the instruction descriptor's Generic flag when deduplicating LLT annotations so target-specific generic pseudos follow LLVM MIR spelling.
| -rw-r--r-- | backend/lib/CodeGen/MIRPrinter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backend/lib/CodeGen/MIRPrinter.cpp b/backend/lib/CodeGen/MIRPrinter.cpp index 1ba8ac1..5eb244a 100644 --- a/backend/lib/CodeGen/MIRPrinter.cpp +++ b/backend/lib/CodeGen/MIRPrinter.cpp @@ -2838,8 +2838,8 @@ Expected<void> BodyPrinter::printInstruction(const MachineInstr &Instruction) { continue; } bool PrintVirtualType = true; - if (isGenericOpcode(Instruction.opcode()) && !Descriptor->Flags.has(InstructionFlag::Phi) && - Index < Descriptor->Operands.size()) { + if (Descriptor->Flags.has(InstructionFlag::Generic) && + !Descriptor->Flags.has(InstructionFlag::Phi) && Index < Descriptor->Operands.size()) { const std::optional<OperandTypeConstraint> &UseConstraint = Descriptor->Operands[Index].TypeConstraint; if (UseConstraint) { |