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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-01 13:09:30 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-01 13:09:30 +0800
commit8553df97bbc6154dae9d0ad861857e71a0efa420 (patch)
tree754fa62b6181e96ed60f1f918c4ee44229d4e0d7 /backend/include/rcc/CodeGen/InstructionDescriptor.h
parentb4d1ddb99e1305f6ea6217e7570dda2a94b16e51 (diff)
downloadrcc-project-8553df97bbc6154dae9d0ad861857e71a0efa420.tar.gz
rcc-project-8553df97bbc6154dae9d0ad861857e71a0efa420.tar.xz
[CodeGen] Add transactional MachineIR builder
Validate insertion cursors, operand ownership, descriptor constraints, ties, implicit registers, and memory operands before allocating or publishing an instruction. Share instruction legality checks with the verifier path and preserve deterministic insertion order.
Diffstat (limited to 'backend/include/rcc/CodeGen/InstructionDescriptor.h')
-rw-r--r--backend/include/rcc/CodeGen/InstructionDescriptor.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/backend/include/rcc/CodeGen/InstructionDescriptor.h b/backend/include/rcc/CodeGen/InstructionDescriptor.h
index c6049b9..94ea374 100644
--- a/backend/include/rcc/CodeGen/InstructionDescriptor.h
+++ b/backend/include/rcc/CodeGen/InstructionDescriptor.h
@@ -23,6 +23,7 @@
namespace rcc {
class MachineInstr;
+class MachineMemOperand;
class MachineRegisterInfo;
class OperandKindSet final {
@@ -217,6 +218,13 @@ struct ImmediatePredicate final {
std::function<bool(const MachineOperand &)> Predicate;
};
+struct MachineOperandTie final {
+ std::size_t DefOperand;
+ std::size_t UseOperand;
+
+ friend bool operator==(MachineOperandTie Left, MachineOperandTie Right) noexcept = default;
+};
+
class InstructionSet final {
public:
[[nodiscard]] static Expected<InstructionSet>
@@ -232,6 +240,15 @@ public:
[[nodiscard]] Expected<void> validateExplicitOperands(Opcode InstructionOpcode,
std::span<const MachineOperand> Operands,
const MachineRegisterInfo &RegInfo) const;
+ [[nodiscard]] Expected<void> validateOperandTies(Opcode InstructionOpcode,
+ std::span<const MachineOperand> ExplicitOperands,
+ std::span<const MachineOperandTie> Ties) const;
+ [[nodiscard]] Expected<void>
+ validateImplicitOperands(Opcode InstructionOpcode,
+ std::span<const MachineOperand *const> ImplicitOperands) const;
+ [[nodiscard]] Expected<void>
+ validateMemOperands(Opcode InstructionOpcode,
+ std::span<const MachineMemOperand *const> MemOperands) const;
[[nodiscard]] Expected<void> validateInstruction(const MachineInstr &Instruction,
const MachineRegisterInfo &RegInfo) const;
@@ -248,6 +265,15 @@ private:
[[nodiscard]] Expected<void> validateExplicitOperands(const InstructionDescriptor &Descriptor,
std::span<const MachineOperand> Operands,
const MachineRegisterInfo &RegInfo) const;
+ [[nodiscard]] Expected<void> validateOperandTies(const InstructionDescriptor &Descriptor,
+ std::span<const MachineOperand> ExplicitOperands,
+ std::span<const MachineOperandTie> Ties) const;
+ [[nodiscard]] Expected<void>
+ validateImplicitOperands(const InstructionDescriptor &Descriptor,
+ std::span<const MachineOperand *const> ImplicitOperands) const;
+ [[nodiscard]] Expected<void>
+ validateMemOperands(const InstructionDescriptor &Descriptor,
+ std::span<const MachineMemOperand *const> MemOperands) const;
[[nodiscard]] Expected<void> validateOperand(const OperandDescriptor &Descriptor,
const MachineOperand &Operand,
const MachineRegisterInfo &RegInfo) const;