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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-24 17:30:29 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-24 17:30:29 +0800 |
| commit | 81afb6570000472c182e5b1f540f69382602aaad (patch) | |
| tree | 4fdab5a642e5088cd456662d438e96d195fdc3d4 /backend/include/rcc/Target/RISCV | |
| parent | 47d0d5140b4616ae4dd7c6d2c3c089ccbfc3b009 (diff) | |
| download | rcc-project-81afb6570000472c182e5b1f540f69382602aaad.tar.gz rcc-project-81afb6570000472c182e5b1f540f69382602aaad.tar.xz | |
[RISCV] Match LLVM emergency spill layout
Diffstat (limited to 'backend/include/rcc/Target/RISCV')
| -rw-r--r-- | backend/include/rcc/Target/RISCV/RISCVPipeline.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/backend/include/rcc/Target/RISCV/RISCVPipeline.h b/backend/include/rcc/Target/RISCV/RISCVPipeline.h index 21a4461..50a6a68 100644 --- a/backend/include/rcc/Target/RISCV/RISCVPipeline.h +++ b/backend/include/rcc/Target/RISCV/RISCVPipeline.h @@ -25,6 +25,7 @@ struct RISCVPipelineOptions final { bool UseTargetCopyInstructions = false; GlobalISelAbortMode GlobalISelAbort = GlobalISelAbortMode::Enable; bool DebugMachineScheduler = false; + bool DebugPrologueEpilogue = false; }; [[nodiscard]] Expected<void> addCanonicalPipeline(MachineFunctionPassManager &Pipeline, |