[RISCV] Consolidate instruction behavior in RISCVInstrInfo

6 files changed, 31 insertions, 54 deletions

diff --git a/backend/include/rcc/CodeGen/MachineCopyPropagation.h b/backend/include/rcc/CodeGen/MachineCopyPropagation.h
index e8ee788..43baa7e 100644
--- a/backend/include/rcc/CodeGen/MachineCopyPropagation.h
+++ b/backend/include/rcc/CodeGen/MachineCopyPropagation.h
@@ -10,7 +10,7 @@
 
 namespace rcc {
 
-class TargetSSAInfo;
+class TargetInstrInfo;
 
 enum class MachineCopyPropagationStage : std::uint8_t {
   PreRegisterAllocation,
@@ -23,7 +23,7 @@ struct MachineCopyPropagationOptions final {
 
 class MachineCopyPropagationPass final : public MachineFunctionPass {
 public:
-  MachineCopyPropagationPass(const TargetSSAInfo &Info, MachineCopyPropagationStage Stage,
+  MachineCopyPropagationPass(const TargetInstrInfo &Info, MachineCopyPropagationStage Stage,
                              MachineCopyPropagationOptions Options = {}) noexcept
       : Info(&Info), Stage(Stage), Options(Options) {}
 
@@ -37,7 +37,7 @@ private:
                                                               const TargetDescription &Target,
                                                               MachineActionReplay &Actions) const;
 
-  const TargetSSAInfo *Info;
+  const TargetInstrInfo *Info;
   MachineCopyPropagationStage Stage;
   MachineCopyPropagationOptions Options;
 };
diff --git a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
index 2cf1bcd..10bcbc6 100644
--- a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
+++ b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
@@ -13,16 +13,14 @@ class TargetMachineCombinerInfo;
 class TargetMemoryFoldingInfo;
 class TargetPseudoExpansionInfo;
 class TargetSchedulingModel;
-class TargetSSAInfo;
 
 struct MachineOptimizationPipelineTargetInfo final {
-  const TargetSSAInfo &SSA;
+  const TargetInstrInfo &InstrInfo;
   const TargetMachineCombinerInfo &Combiner;
   const TargetMemoryFoldingInfo &MemoryFolding;
   const TargetFrameLowering &FrameLowering;
   const TargetPseudoExpansionInfo &PseudoExpansion;
   const TargetSchedulingModel &SchedulingModel;
-  const TargetInstrInfo &BranchInfo;
 };
 
 [[nodiscard]] Expected<void> registerMachineOptimizationAnalyses(MachineAnalysisManager &Analyses);
diff --git a/backend/include/rcc/CodeGen/MachineSSAExit.h b/backend/include/rcc/CodeGen/MachineSSAExit.h
index fdf74f0..4b6966d 100644
--- a/backend/include/rcc/CodeGen/MachineSSAExit.h
+++ b/backend/include/rcc/CodeGen/MachineSSAExit.h
@@ -4,14 +4,14 @@
 #define RCC_CODEGEN_MACHINESSAEXIT_H
 
 #include "rcc/CodeGen/MachinePass.h"
-#include "rcc/CodeGen/TargetCodeGen.h"
+#include "rcc/CodeGen/TargetInstrInfo.h"
 
 namespace rcc {
 
 class PHIEliminationPass final : public MachineFunctionPass {
 public:
   PHIEliminationPass() noexcept = default;
-  explicit PHIEliminationPass(const TargetSSAInfo &Info) noexcept : Info(&Info) {}
+  explicit PHIEliminationPass(const TargetInstrInfo &Info) noexcept : Info(&Info) {}
 
   [[nodiscard]] const MachinePassContract &contract() const noexcept override;
   [[nodiscard]] Expected<MachinePassResult> run(MachineFunction &Function,
@@ -23,13 +23,13 @@ private:
                                                               const TargetDescription &Target,
                                                               MachineActionReplay &Actions);
 
-  const TargetSSAInfo *Info = nullptr;
+  const TargetInstrInfo *Info = nullptr;
 };
 
 class TwoAddressRewritePass final : public MachineFunctionPass {
 public:
   TwoAddressRewritePass() noexcept = default;
-  explicit TwoAddressRewritePass(const TargetSSAInfo &Info) noexcept : Info(&Info) {}
+  explicit TwoAddressRewritePass(const TargetInstrInfo &Info) noexcept : Info(&Info) {}
 
   [[nodiscard]] const MachinePassContract &contract() const noexcept override;
   [[nodiscard]] Expected<MachinePassResult> run(MachineFunction &Function,
@@ -41,7 +41,7 @@ private:
                                                               const TargetDescription &Target,
                                                               MachineActionReplay &Actions);
 
-  const TargetSSAInfo *Info = nullptr;
+  const TargetInstrInfo *Info = nullptr;
 };
 
 } // namespace rcc
diff --git a/backend/include/rcc/CodeGen/TargetCodeGen.h b/backend/include/rcc/CodeGen/TargetCodeGen.h
index 34a6de4..65f65a4 100644
--- a/backend/include/rcc/CodeGen/TargetCodeGen.h
+++ b/backend/include/rcc/CodeGen/TargetCodeGen.h
@@ -3,20 +3,14 @@
 #ifndef RCC_CODEGEN_TARGETCODEGEN_H
 #define RCC_CODEGEN_TARGETCODEGEN_H
 
-#include "rcc/CodeGen/MachineIRTypes.h"
-#include "rcc/CodeGen/Register.h"
 #include "rcc/Support/Error.h"
 
-#include <cstddef>
 #include <cstdint>
-#include <optional>
 
 namespace rcc {
 
 class MachineFunction;
-class MachineBasicBlock;
 class MachineInstr;
-class MachineRegisterInfo;
 class TargetDescription;
 struct VirtualRegisterInfo;
 
@@ -96,38 +90,6 @@ public:
   }
 };
 
-class TargetSSAInfo {
-public:
-  virtual ~TargetSSAInfo() = default;
-
-  [[nodiscard]] virtual Expected<bool> isFallthroughEdge(const MachineBasicBlock &From,
-                                                         const MachineBasicBlock &To,
-                                                         const MachineFunction &Function,
-                                                         const TargetDescription &Target) const = 0;
-
-  [[nodiscard]] virtual Expected<bool>
-  rewriteBranchTarget(MachineBasicBlock &Block, MachineBasicBlock &OldTarget,
-                      MachineBasicBlock &NewTarget, MachineFunction &Function,
-                      const TargetDescription &Target) const = 0;
-
-  [[nodiscard]] virtual Expected<void>
-  insertUnconditionalBranch(MachineBasicBlock &Block, MachineBasicBlock &Target,
-                            MachineFunction &Function,
-                            const TargetDescription &TargetDescription) const = 0;
-
-  [[nodiscard]] virtual Expected<void> validateCopy(Register Destination,
-                                                    SubRegIndex DestinationSubReg, Register Source,
-                                                    SubRegIndex SourceSubReg,
-                                                    const MachineFunction &Function,
-                                                    const TargetDescription &Target) const = 0;
-
-  [[nodiscard]] virtual Expected<bool> tryConvertToThreeAddress(MachineInstr &, std::size_t,
-                                                                std::size_t, MachineFunction &,
-                                                                const TargetDescription &) const {
-    return false;
-  }
-};
-
 } // namespace rcc
 
 #endif // RCC_CODEGEN_TARGETCODEGEN_H
diff --git a/backend/include/rcc/CodeGen/TargetInstrInfo.h b/backend/include/rcc/CodeGen/TargetInstrInfo.h
index d9f0906..34752c5 100644
--- a/backend/include/rcc/CodeGen/TargetInstrInfo.h
+++ b/backend/include/rcc/CodeGen/TargetInstrInfo.h
@@ -3,8 +3,11 @@
 #ifndef RCC_CODEGEN_TARGETINSTRINFO_H
 #define RCC_CODEGEN_TARGETINSTRINFO_H
 
+#include "rcc/CodeGen/MachineIRTypes.h"
+#include "rcc/CodeGen/Register.h"
 #include "rcc/Support/Error.h"
 
+#include <cstddef>
 #include <cstdint>
 #include <optional>
 
@@ -40,8 +43,25 @@ public:
                       MachineBasicBlock &NewTarget, MachineFunction &Function,
                       const TargetDescription &Target) const = 0;
   [[nodiscard]] virtual Expected<MachineInstr *>
-  insertUnconditionalBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock,
-                            MachineFunction &Function, const TargetDescription &Target) const = 0;
+  insertBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock, MachineFunction &Function,
+               const TargetDescription &Target) const = 0;
+
+  [[nodiscard]] virtual Expected<bool> isFallthroughEdge(const MachineBasicBlock &From,
+                                                         const MachineBasicBlock &To,
+                                                         const MachineFunction &Function,
+                                                         const TargetDescription &Target) const = 0;
+
+  [[nodiscard]] virtual Expected<void> validateCopy(Register Destination,
+                                                    SubRegIndex DestinationSubReg, Register Source,
+                                                    SubRegIndex SourceSubReg,
+                                                    const MachineFunction &Function,
+                                                    const TargetDescription &Target) const = 0;
+
+  [[nodiscard]] virtual Expected<bool> tryConvertToThreeAddress(MachineInstr &, std::size_t,
+                                                                std::size_t, MachineFunction &,
+                                                                const TargetDescription &) const {
+    return false;
+  }
 
   [[nodiscard]] virtual Expected<std::uint32_t>
   instructionSize(const MachineInstr &Instruction, const MachineFunction &Function,
diff --git a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
index d68157a..6cda815 100644
--- a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
+++ b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
@@ -7,7 +7,6 @@
 #include "rcc/CodeGen/MachineOptimizationPipeline.h"
 #include "rcc/CodeGen/TargetCodeGen.h"
 #include "rcc/CodeGen/TargetFrameLowering.h"
-#include "rcc/CodeGen/TargetInstrInfo.h"
 #include "rcc/CodeGen/TargetMemoryFolding.h"
 #include "rcc/CodeGen/TargetPseudoExpansion.h"
 #include "rcc/CodeGen/TargetRegisterAllocationInfo.h"
@@ -23,13 +22,11 @@ namespace rcc::riscv {
 createLegalizerInfo(RISCVSubtargetFeatures Features);
 [[nodiscard]] const TargetRegisterBankInfo &registerBankInfo() noexcept;
 [[nodiscard]] const TargetInstructionSelector &instructionSelector() noexcept;
-[[nodiscard]] const TargetSSAInfo &ssaInfo() noexcept;
 [[nodiscard]] const TargetRegisterAllocationInfo &registerAllocationInfo() noexcept;
 [[nodiscard]] const TargetFrameLowering &frameLowering() noexcept;
 [[nodiscard]] const TargetSchedulingModel &schedulingModel() noexcept;
 [[nodiscard]] const TargetMachineCombinerInfo &machineCombinerInfo() noexcept;
 [[nodiscard]] const TargetMemoryFoldingInfo &memoryFoldingInfo() noexcept;
-[[nodiscard]] const TargetInstrInfo &branchInfo() noexcept;
 [[nodiscard]] const TargetPseudoExpansionInfo &pseudoExpansionInfo() noexcept;
 [[nodiscard]] MachineOptimizationPipelineTargetInfo optimizationPipelineInfo() noexcept;