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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-22 18:59:22 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-22 18:59:22 +0800
commit36b0be1ec1558f88d4f031a1817c3a4c2cba07a6 (patch)
tree3cf29b19ec7e450bd04dca8d416d68350aa20de2 /backend/lib/CodeGen/MIRPrinter.cpp
parent8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7 (diff)
downloadrcc-project-36b0be1ec1558f88d4f031a1817c3a4c2cba07a6.tar.gz
rcc-project-36b0be1ec1558f88d4f031a1817c3a4c2cba07a6.tar.xz
[CodeGen] Match LLVM machine debug stripping
Diffstat (limited to 'backend/lib/CodeGen/MIRPrinter.cpp')
-rw-r--r--backend/lib/CodeGen/MIRPrinter.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/backend/lib/CodeGen/MIRPrinter.cpp b/backend/lib/CodeGen/MIRPrinter.cpp
index 5eb244a..c684368 100644
--- a/backend/lib/CodeGen/MIRPrinter.cpp
+++ b/backend/lib/CodeGen/MIRPrinter.cpp
@@ -1935,7 +1935,8 @@ Expected<void> BodyPrinter::printRegisterOperand(const MachineOperand &Operand,
Output.append("internal ");
if (Flags.has(RegisterOperandFlag::EarlyClobber))
Output.append("early-clobber ");
- if (Flags.has(RegisterOperandFlag::Debug))
+ if (Flags.has(RegisterOperandFlag::Debug) &&
+ (Operand.parent() == nullptr || !Operand.parent()->isDebugInstr()))
Output.append("debug-use ");
if (Flags.has(RegisterOperandFlag::Renamable))
Output.append("renamable ");