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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-13 18:52:39 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-13 18:52:39 +0800
commit5794302adc3ce94c69318965b1bbef7a895d5d41 (patch)
tree908bae4ae06efd1681ec64824e8c6e6648808ef8 /backend/lib/CodeGen/MIRPrinter.cpp
parentdbe314ea93f80eba33579d7b72f3aadd0d510cb5 (diff)
downloadrcc-project-5794302adc3ce94c69318965b1bbef7a895d5d41.tar.gz
rcc-project-5794302adc3ce94c69318965b1bbef7a895d5d41.tar.xz
[CodeGen] Preserve LLT annotations on generic opcodes
Diffstat (limited to 'backend/lib/CodeGen/MIRPrinter.cpp')
-rw-r--r--backend/lib/CodeGen/MIRPrinter.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/backend/lib/CodeGen/MIRPrinter.cpp b/backend/lib/CodeGen/MIRPrinter.cpp
index d8a6945..9008315 100644
--- a/backend/lib/CodeGen/MIRPrinter.cpp
+++ b/backend/lib/CodeGen/MIRPrinter.cpp
@@ -2,6 +2,7 @@
#include "rcc/CodeGen/MIRPrinter.h"
+#include "rcc/CodeGen/GenericOpcodes.h"
#include "rcc/CodeGen/InlineAsm.h"
#include "rcc/CodeGen/InstructionDescriptor.h"
#include "rcc/CodeGen/MIRYamlMapping.h"
@@ -2877,8 +2878,8 @@ Expected<void> BodyPrinter::printInstruction(const MachineInstr &Instruction) {
continue;
}
bool PrintVirtualType = true;
- if (Descriptor->Flags.has(InstructionFlag::Generic) &&
- !Descriptor->Flags.has(InstructionFlag::Phi) && Index < Descriptor->Operands.size()) {
+ if (isGenericOpcode(Instruction.opcode()) && !Descriptor->Flags.has(InstructionFlag::Phi) &&
+ Index < Descriptor->Operands.size()) {
const std::optional<OperandTypeConstraint> &UseConstraint =
Descriptor->Operands[Index].TypeConstraint;
if (UseConstraint) {