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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-13 23:55:38 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-13 23:55:38 +0800
commitaa69e15c6909c3b162b15f5326f0a72ba9bb7163 (patch)
tree6428eb20e41bad1fc8ad2f5c259bc5537f54554d /backend/lib/CodeGen/MachineVerifier.cpp
parentcd30fb546e389d1fb78ce8e579b3dba3a8fdb52a (diff)
downloadrcc-project-aa69e15c6909c3b162b15f5326f0a72ba9bb7163.tar.gz
rcc-project-aa69e15c6909c3b162b15f5326f0a72ba9bb7163.tar.xz
[CodeGen] Unify scalar low-level types
Diffstat (limited to 'backend/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r--backend/lib/CodeGen/MachineVerifier.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/backend/lib/CodeGen/MachineVerifier.cpp b/backend/lib/CodeGen/MachineVerifier.cpp
index 725a288..14ce8ef 100644
--- a/backend/lib/CodeGen/MachineVerifier.cpp
+++ b/backend/lib/CodeGen/MachineVerifier.cpp
@@ -849,7 +849,7 @@ private:
MissingVirtualBank |= !Info.Bank;
MissingVirtualClass |= !Info.RegClass;
if (Info.Type && !Info.Type->isValid())
- return fail("virtual register has an invalid LLT");
+ return fail("virtual register has an invalid LowLevelType");
std::unordered_set<PhysicalRegister> Hints;
for (const PhysicalRegister Hint : Info.AllocationHints) {
@@ -924,7 +924,7 @@ private:
Has(MachineFunctionProperty::Legalized) ||
Has(MachineFunctionProperty::RegBankSelected);
if (NeedsTypes && MissingVirtualType)
- return fail("typed pipeline stage has a virtual register without LLT");
+ return fail("typed pipeline stage has a virtual register without LowLevelType");
if (Options.Mode == MachineVerifierMode::PreLegalizer) {
if (!Has(MachineFunctionProperty::IsSSA) || !Has(MachineFunctionProperty::TracksLiveness)) {