[CodeGen] Add machine IR value semantics

Add strongly typed machine indices, lane masks, instruction flags, fixed-point branch probabilities, and preserved-register masks.

Model immutable machine memory operands with explicit base identity, size, alignment, address space, alias information, and validated atomic operation and ordering rules. Cover normal, boundary, and invalid combinations in standalone tests.

1 files changed, 21 insertions, 0 deletions

diff --git a/backend/lib/CodeGen/RegisterMask.cpp b/backend/lib/CodeGen/RegisterMask.cpp
new file mode 100644
index 0000000..027ee26
--- /dev/null
+++ b/backend/lib/CodeGen/RegisterMask.cpp
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#include "rcc/CodeGen/RegisterMask.h"
+
+namespace rcc {
+
+bool RegisterMask::preserves(PhysicalRegister PhysReg) const noexcept {
+  if (!PhysReg.isValid())
+    return false;
+
+  constexpr std::uint32_t BitsPerWord = 64;
+  const std::uint32_t RegisterNumber = PhysReg.number();
+  const std::size_t WordIndex = RegisterNumber / BitsPerWord;
+  if (WordIndex >= PreservedWords.size())
+    return false;
+
+  const std::uint32_t BitIndex = RegisterNumber % BitsPerWord;
+  return (PreservedWords[WordIndex] & (std::uint64_t{1} << BitIndex)) != 0;
+}
+
+} // namespace rcc