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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-08 04:14:34 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-08 04:14:34 +0800
commit77884c967d1cbc48afcbaef7e5a35adcb3c5da1b (patch)
tree8cc31c1c5115ed909ec9f8751964bfdc96fbd4ad /backend/lib/CodeGen/TargetDescription.cpp
parent10b7e69448f866bcd6893b21d7f78d766252eb11 (diff)
downloadrcc-project-77884c967d1cbc48afcbaef7e5a35adcb3c5da1b.tar.gz
rcc-project-77884c967d1cbc48afcbaef7e5a35adcb3c5da1b.tar.xz
[CodeGen] Implement machine SSA exit
Diffstat (limited to 'backend/lib/CodeGen/TargetDescription.cpp')
-rw-r--r--backend/lib/CodeGen/TargetDescription.cpp8
1 files changed, 7 insertions, 1 deletions
diff --git a/backend/lib/CodeGen/TargetDescription.cpp b/backend/lib/CodeGen/TargetDescription.cpp
index e2bbe8a..e8c7d79 100644
--- a/backend/lib/CodeGen/TargetDescription.cpp
+++ b/backend/lib/CodeGen/TargetDescription.cpp
@@ -58,7 +58,13 @@ Expected<TargetDescription> TargetDescription::create(InstructionSet Instruction
for (const InstructionDescriptor &Instruction : Instructions.descriptors()) {
for (const OperandDescriptor &Operand : Instruction.Operands) {
- if ((Operand.AllowedTargetFlags & ~MIRText->serializableOperandFlagMask()) != 0) {
+ if (Operand.AllowAnyTargetFlags && Operand.AllowedTargetFlags != 0) {
+ return makeUnexpected(
+ ErrorCode::InvalidArgument,
+ "instruction operand cannot combine unrestricted and explicit target flags");
+ }
+ if (!Operand.AllowAnyTargetFlags &&
+ (Operand.AllowedTargetFlags & ~MIRText->serializableOperandFlagMask()) != 0) {
return makeUnexpected(
ErrorCode::InvalidArgument,
"instruction operand allows a target flag outside the MIR text schema");