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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-13 23:55:38 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-13 23:55:38 +0800
commitaa69e15c6909c3b162b15f5326f0a72ba9bb7163 (patch)
tree6428eb20e41bad1fc8ad2f5c259bc5537f54554d /backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
parentcd30fb546e389d1fb78ce8e579b3dba3a8fdb52a (diff)
downloadrcc-project-aa69e15c6909c3b162b15f5326f0a72ba9bb7163.tar.gz
rcc-project-aa69e15c6909c3b162b15f5326f0a72ba9bb7163.tar.xz
[CodeGen] Unify scalar low-level types
Diffstat (limited to 'backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp')
-rw-r--r--backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp15
1 files changed, 5 insertions, 10 deletions
diff --git a/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 7c60219..66a3371 100644
--- a/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -20,13 +20,9 @@
namespace rcc::riscv {
namespace {
-[[nodiscard]] bool isRVFloatType(LLT Type) noexcept {
- return Type.isFloat() && (Type.scalarBitWidth() == 32 || Type.scalarBitWidth() == 64);
-}
-
-[[nodiscard]] bool isScalarGPRType(LLT Type) noexcept {
+[[nodiscard]] bool isScalarGPRType(LowLevelType Type) noexcept {
return (Type.isPointer() && Type.addressSpace() == 0 && Type.scalarBitWidth() == 64) ||
- ((Type.isInteger() || Type.isAnyScalar()) && Type.scalarBitWidth() >= 1 &&
+ (Type.isCategoryNeutralScalar() && Type.scalarBitWidth() >= 1 &&
Type.scalarBitWidth() <= 64);
}
@@ -219,9 +215,9 @@ requiredBankForRegister(const MachineFunction &Function, Register Reg,
"RISC-V selection requires a type for every virtual register");
}
const VirtualRegisterInfo &RegisterInfo = Info->get();
- const LLT Type = RegisterInfo.Type.value_or(LLT{});
+ const LowLevelType Type = RegisterInfo.Type.value_or(LowLevelType{});
RegisterClassID RequiredClass;
- if ((RegisterInfo.Bank && *RegisterInfo.Bank == fprBank()) || Type.isFloat()) {
+ if (RegisterInfo.Bank && *RegisterInfo.Bank == fprBank()) {
if (Type.scalarBitWidth() != 32 && Type.scalarBitWidth() != 64) {
return makeUnexpected(ErrorCode::Unsupported,
"RISC-V RV64GC has no floating register class for type '" +
@@ -269,8 +265,7 @@ RISCVRegisterBankInfo::selectBank(const MachineFunction &Function, Register Reg,
if (!Required)
return std::unexpected(Required.error());
const bool IsConstrained = Required->has_value() || Info.Bank.has_value();
- const RegisterBankID Selected =
- Required->value_or(isRVFloatType(*Info.Type) ? fprBank() : gprBank());
+ const RegisterBankID Selected = Required->value_or(gprBank());
if (Info.Bank && *Info.Bank != Selected) {
return makeUnexpected(ErrorCode::VerificationError,
"RISC-V virtual register has a conflicting register bank");