[RISCV][GlobalISel] Generate indirect branch selection

1 files changed, 0 insertions, 15 deletions

diff --git a/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 1e2eb92..ce6400e 100644
--- a/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/backend/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -478,8 +478,6 @@ public:
       return selectAtomicRMW(Instruction, Function, Target, Type, Generic);
     case GenericOpcode::G_FENCE:
       return selectFence(Instruction);
-    case GenericOpcode::G_BRINDIRECT:
-      return selectIndirectBranch(Instruction);
     case GenericOpcode::G_TRAP:
     case GenericOpcode::G_DEBUGTRAP:
     case GenericOpcode::G_UBSANTRAP:
@@ -1198,19 +1196,6 @@ private:
     return Instruction.setOpcode(instructionOpcode(InstructionOpcode::FENCE));
   }
 
-  [[nodiscard]] Expected<void> selectIndirectBranch(MachineInstr &Instruction) const {
-    auto Zero = physicalRegister(PhysicalRegisterID::X0);
-    if (!Zero)
-      return std::unexpected(Zero.error());
-    auto Inserted = insertPhysicalRegister(Instruction, 0, *Zero, RegisterOperandFlag::Define);
-    if (!Inserted)
-      return std::unexpected(Inserted.error());
-    auto Immediate = appendImmediate(Instruction, 0);
-    if (!Immediate)
-      return std::unexpected(Immediate.error());
-    return Instruction.setOpcode(instructionOpcode(InstructionOpcode::JALR));
-  }
-
   [[nodiscard]] Expected<void> selectTrap(MachineInstr &Instruction) const {
     while (Instruction.operandCount() != 0) {
       auto Erased = Instruction.eraseOperand(Instruction.operandCount() - 1U);