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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 00:26:10 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 00:26:10 +0800 |
| commit | d91d57297bdb30b6363e259ab75d517dc333e292 (patch) | |
| tree | b931c72127e25a4acbf1f7b38ffdcba74ef270c7 /backend/lib/Target/RISCV/RISCV.rccdesc | |
| parent | adf3e4f02e330e052dbb75e9601bae5273ccfe6c (diff) | |
| download | rcc-project-d91d57297bdb30b6363e259ab75d517dc333e292.tar.gz rcc-project-d91d57297bdb30b6363e259ab75d517dc333e292.tar.xz | |
[RISCV] Support absolute address operand flags
Diffstat (limited to 'backend/lib/Target/RISCV/RISCV.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCV.rccdesc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc index 5000d8b..5ef719b 100644 --- a/backend/lib/Target/RISCV/RISCV.rccdesc +++ b/backend/lib/Target/RISCV/RISCV.rccdesc @@ -277,13 +277,15 @@ register_masks: preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, F8_D, F9_D, F18_D, F19_D, F20_D, F21_D, F22_D, F23_D, F24_D, F25_D, F26_D, F27_D, F8_F, F9_F, F18_F, F19_F, F20_F, F21_F, F22_F, F23_F, F24_F, F25_F, F26_F, F27_F] mir_operand_flags: - direct_mask: 31 + direct_mask: 127 direct: - { name: riscv-call, value: 1 } - { name: riscv-pcrel-hi, value: 2 } - { name: riscv-pcrel-lo, value: 4 } - { name: riscv-copy-f32, value: 8 } - { name: riscv-copy-f64, value: 16 } + - { name: riscv-hi, value: 32 } + - { name: riscv-lo, value: 64 } bitmask: [] calling_conventions: @@ -429,7 +431,7 @@ instructions: encoding: 5175 operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [immediate], immediate_predicate: SIMM20, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM20, allowed_target_flags: 32, name: IMM } num_explicit_defs: 1 flags: [produces_code, rematerializable] scheduling_class: ALU @@ -458,7 +460,7 @@ instructions: operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - - { kinds: [immediate], immediate_predicate: SIMM12, name: IMM } + - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 68, name: IMM } num_explicit_defs: 1 flags: [produces_code, rematerializable] scheduling_class: ALU |