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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 01:43:04 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 01:43:04 +0800 |
| commit | 9e89d1d718977749ca798b27b7ad45e1781602c2 (patch) | |
| tree | e4ab1a06bb0f742792474153071bad94ff279f06 /backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc | |
| parent | b8fb9248e77e492c630ca135d1bfd58b74f9752a (diff) | |
| download | rcc-project-9e89d1d718977749ca798b27b7ad45e1781602c2.tar.gz rcc-project-9e89d1d718977749ca798b27b7ad45e1781602c2.tar.xz | |
[RISCV] Implement Zcmp move merging
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc index fa1b75a..7f5c3c5 100644 --- a/backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc +++ b/backend/lib/Target/RISCV/RISCVInstrInfoC.rccdesc @@ -513,3 +513,33 @@ instructions: scheduling_class: STORE encoding_category: C assembly_format: RS2_OFFSET_SP + - + id: 1270 + symbol: CM_MVA01S + name: CM_MVA01S + assembly_mnemonic: cm.mva01s + encoding: 44130 + operands: + - { kinds: [register], role: use, register_class: SR07, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: SR07, register_bank: GPR, name: RS2 } + num_explicit_defs: 0 + flags: [produces_code] + implicit_defs: [{ register: X10 }, { register: X11 }] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 + - + id: 1271 + symbol: CM_MVSA01 + name: CM_MVSA01 + assembly_mnemonic: cm.mvsa01 + encoding: 44066 + operands: + - { kinds: [register], role: def, register_class: SR07, register_bank: GPR, name: RD } + - { kinds: [register], role: def, register_class: SR07, register_bank: GPR, name: RS2 } + num_explicit_defs: 2 + flags: [produces_code] + implicit_uses: [{ register: X10 }, { register: X11 }] + scheduling_class: COMPRESSED + encoding_category: C + assembly_format: RD_RS2 |