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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-24 18:50:21 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-24 18:50:21 +0800 |
| commit | b9ef2aac9a9e868fea961078d62e46aab91e462d (patch) | |
| tree | bb5b40a134ff9dbde0ea81bbc1df5f375da71af2 /backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc | |
| parent | bcc6c1b99baf8781f0bad32915806a7b638a170a (diff) | |
| download | rcc-project-b9ef2aac9a9e868fea961078d62e46aab91e462d.tar.gz rcc-project-b9ef2aac9a9e868fea961078d62e46aab91e462d.tar.xz | |
[RISCV] Implement save and restore libcalls
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc index 3e458df..41cc051 100644 --- a/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc +++ b/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc @@ -336,6 +336,20 @@ instructions: owner: post_ra_expansion deadline: post_ra_finalized - + id: 1269 + symbol: PseudoCALLReg + name: PseudoCALLReg + operands: + - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } + - { kinds: [global_symbol, external_symbol], allowed_target_flags: 1 } + - { kinds: [register_mask], optional: true } + num_explicit_defs: 1 + allow_extra_implicit_operands: true + flags: [pseudo, produces_code, allowed_pre_legalizer, call, may_load, may_store, has_side_effects, not_duplicable, unmodeled_side_effects] + size: 8 + owner: post_ra_expansion + deadline: post_ra_finalized + - id: 1224 symbol: PseudoRET name: PseudoRET @@ -357,7 +371,7 @@ instructions: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [immediate, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } - - { kinds: [register_mask] } + - { kinds: [register_mask], optional: true } num_explicit_defs: 1 allow_extra_implicit_operands: true flags: [call, may_load, may_store, has_side_effects, produces_code, not_duplicable, unmodeled_side_effects] @@ -374,7 +388,7 @@ instructions: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [immediate, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 4, name: IMM } - - { kinds: [register_mask] } + - { kinds: [register_mask], optional: true } num_explicit_defs: 1 allow_extra_implicit_operands: true flags: [terminator, branch, indirect_branch, call, barrier, may_load, may_store, has_side_effects, produces_code, not_duplicable, unmodeled_side_effects] |