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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-28 19:15:07 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-28 19:15:07 +0800 |
| commit | b1c08d57f1637f5ee813d1409dacdfa88c1509a0 (patch) | |
| tree | d1c8d3f9ba3da70628e356dcd97f878ea7124b62 /backend/lib/Target/RISCV/RISCVInstrInfoZcmp.rccdesc | |
| parent | f89d528efc0228c049c2867dcba886a56bac8619 (diff) | |
| download | rcc-project-b1c08d57f1637f5ee813d1409dacdfa88c1509a0.tar.gz rcc-project-b1c08d57f1637f5ee813d1409dacdfa88c1509a0.tar.xz | |
[RISCV] Generate complete Zcmp instruction definitions
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVInstrInfoZcmp.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVInstrInfoZcmp.rccdesc | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoZcmp.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoZcmp.rccdesc new file mode 100644 index 0000000..eb0f822 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVInstrInfoZcmp.rccdesc @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +instructions: + - + id: 1270 + symbol: CM_MVA01S + name: CM_MVA01S + assembly_mnemonic: cm.mva01s + encoding: 44130 + operands: + - { kinds: [register], role: use, register_class: SR07, register_bank: GPR, name: RS1 } + - { kinds: [register], role: use, register_class: SR07, register_bank: GPR, name: RS2 } + num_explicit_defs: 0 + flags: [produces_code] + implicit_defs: [{ register: X10 }, { register: X11 }] + scheduling_class: COMPRESSED + encoding_category: ZCMP_MOVE + assembly_format: RD_RS2 + - + id: 1271 + symbol: CM_MVSA01 + name: CM_MVSA01 + assembly_mnemonic: cm.mvsa01 + encoding: 44066 + operands: + - { kinds: [register], role: def, register_class: SR07, register_bank: GPR, name: RD } + - { kinds: [register], role: def, register_class: SR07, register_bank: GPR, name: RS2 } + num_explicit_defs: 2 + flags: [produces_code] + implicit_uses: [{ register: X10 }, { register: X11 }] + scheduling_class: COMPRESSED + encoding_category: ZCMP_MOVE + assembly_format: RD_RS2 + - + id: 1272 + symbol: CM_PUSH + name: CM_PUSH + assembly_mnemonic: cm.push + encoding: 47106 + operands: + - { kinds: [immediate], immediate_predicate: ZCMP_RLIST, name: RLIST } + - { kinds: [immediate], immediate_predicate: ZCMP_STACKADJ, name: STACKADJ } + num_explicit_defs: 0 + allow_extra_implicit_operands: true + flags: [may_store, produces_code] + implicit_defs: [{ register: X2 }] + implicit_uses: [{ register: X2 }] + scheduling_class: STORE + encoding_category: ZCMP_STACK + assembly_format: RLIST_STACKADJ + - + id: 1273 + symbol: CM_POPRET + name: CM_POPRET + assembly_mnemonic: cm.popret + encoding: 48642 + operands: + - { kinds: [immediate], immediate_predicate: ZCMP_RLIST, name: RLIST } + - { kinds: [immediate], immediate_predicate: ZCMP_STACKADJ, name: STACKADJ } + num_explicit_defs: 0 + allow_extra_implicit_operands: true + flags: [terminator, return, barrier, may_load, produces_code] + implicit_defs: [{ register: X2 }] + implicit_uses: [{ register: X2 }] + scheduling_class: LOAD + encoding_category: ZCMP_STACK + assembly_format: RLIST_STACKADJ + - + id: 1274 + symbol: CM_POPRETZ + name: CM_POPRETZ + assembly_mnemonic: cm.popretz + encoding: 48130 + operands: + - { kinds: [immediate], immediate_predicate: ZCMP_RLIST, name: RLIST } + - { kinds: [immediate], immediate_predicate: ZCMP_STACKADJ, name: STACKADJ } + num_explicit_defs: 0 + allow_extra_implicit_operands: true + flags: [terminator, return, barrier, may_load, produces_code] + implicit_defs: [{ register: X2 }, { register: X10 }] + implicit_uses: [{ register: X2 }] + scheduling_class: LOAD + encoding_category: ZCMP_STACK + assembly_format: RLIST_STACKADJ + - + id: 1275 + symbol: CM_POP + name: CM_POP + assembly_mnemonic: cm.pop + encoding: 47618 + operands: + - { kinds: [immediate], immediate_predicate: ZCMP_RLIST, name: RLIST } + - { kinds: [immediate], immediate_predicate: ZCMP_STACKADJ, name: STACKADJ } + num_explicit_defs: 0 + allow_extra_implicit_operands: true + flags: [may_load, produces_code] + implicit_defs: [{ register: X2 }] + implicit_uses: [{ register: X2 }] + scheduling_class: LOAD + encoding_category: ZCMP_STACK + assembly_format: RLIST_STACKADJ |